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We report high performance (100) and (110) oriented single-grain thin-film-transistors (SG-TFTs) fabricated below 600??C without any seed substrate. The orientation has been contolled by ??-Czochralski process with the excimer laser. Field-effect mobility of n-channel transistor is 998cm2/Vs for (100) SG-TFTs and 811cm2/Vs for (110) SG-TFTs. Field-effect mobility of p-channel transistor is 292cm2/Vs...
A novel five-mask low temperature polycrystalline silicon (LTPS) complementary metal oxide semiconductor (CMOS) structure was verified by manufacturing Thin Film Transistor (TFT) test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed without additional photo mask steps to solve the...
First results of 100 V, novel Trench Super Junction HVTFTs fully compatible to the LTPS technology are presented. They exhibit ON/OFF current ratio of more than 107 with sub-threshold swing of 0.75 V/decade and specific resistance (Rsp) of 40 ??mm2.The influence of geometric parameters on both unipolar and bipolar devices is analysed.
We investigate the role of the 0.5 eV traps in determining GaN HEMT degradation by means of DC and rf testing, and 2D numerical simulation. We demonstrate that generation of deep levels, having an activation energy of 0.5 eV, is responsible for the degradation observed during rf aging; we show that the occurrence of trap-induced degradation depends on rf driving conditions. We also show that degradation...
An in-depth study on the resistive switching mechanism of perovskite oxide based device was performed. Compared with filament type resistive switching device, excellent switching uniformity was obtained due to controlled redox reaction at metal/oxide interface. Electromigration of oxygen ion under the bipolar electric filed can explain the switching behavior. Formation of ultrathin AlOx at the interface...
A 30??30 nm2 HfOx resistance random access memory (RRAM) with excellent electrical performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and one resistor (1T1R) array with robust characteristics was also fabricated successfully. The device yield of the 1 Kb array is 100%, and the endurance for these devices can exceed 106 cycles by a pulse width of 40 ns. Two...
In this paper, we have studied the charge trapping mechanisms of nitride-based non-volatile memories. The impact of different silicon-nitride (SiN) compositions (standard, std, and Si-rich) on the device characteristics has been investigated through material characterizations, electrical measurements, atomistic and electrical simulations. We found that the different physical nature of the dominant...
A novel amorphous oxide TFT Enhancement/Depletion (E/D) inverter through uni-/bi-layer channel hybrid integration with conventional process is demonstrated. The device's threshold voltages (Vth) is strictly controlled and the fabrication technique is specially designed. Comparing to the reported high speed bootstrapped inverter, the output swing, switching voltage gain and noise margin of E/D inverter...
Si, Ge and III-V based MOSFETs can be limited by Fermi level pinning (FLP) at their interfaces. Pinning can arise from either intrinsic (metal induced gap states, MIGs) or extrinsic (defects) mechanisms. Identifying the correct mechanism is not trivial, as both mechanisms follow similar chemical trends. However knowing the correct mechanism is important, as only extrinsic mechanisms can be corrected...
For future high-performance reconfigurable logic devices, we developed a novel spin-based MOSFET; ??Spin-Transfer-Torque-Switching MOSFET (STS-MOSFET)?? that enables the read/write performance and memorization of the configuration with nonvolatility by using the ferromagnetic electrodes and the spin-polarized current through Si channel and spin-transfer torque switching in magnetic tunnel junctions...
We fabricate lithographically patterned graphene nanoribbon structures. The sizes of these energy gaps estimated from the conductance in the nonlinear response regime indicate that the gap is scaling inversely proportional to the width of the ribbons. The temperature dependent conductance measurements suggest the substantial amount of edge disorders in the graphene nanoribbons. We also fabricate the...
Mobility (??) and Lg dependence of high-field velocity (v) is systematically investigated. A wide variety of ?? characteristics are realized with various gate dielectrics of SiO2, SiON, HfLaSiON, and HfLaAlSiON. At Lg = 30 nm, the sensitivities of v to ?? and scaling in Lg, (??v/v)/(????/??) and (??v/v)/(??Lg/Lg), are 0.43 and -0.45, respectively: in quasi-ballistic transport regime, ?? and scaling...
We demonstrate best in class performance for MANOS-type charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiNx charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1st time we combine BE-TO, BE-SiNx, BE-blocking layer (BE-BL) and...
Metallic carbon nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs) resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of...
An enhanced hydrogen and urea biosensor based on a novel flash-ion-sensitive field-effect transistor (FISFET) with HfO2/Gd2O3(Gd) nano-crystal/SiO2 sensing membrane is demonstrated experimentally. The super Nernstian phenomenon of hydrogen detection (~80 mV/pH) is achieved according to the charge trapping effect. The performance of reliability including long-term stability and endurance are systematic...
The low level of output signal in conventional silicon nanowire field-effect transistors (FETs) could limit their potential deployments as integrated chemical and biomedical sensors. We have proposed in this work a novel T-shape channel nanowire FET with a built-in signal amplification mechanism. Compared to the co-fabricated, conventional silicon nanowire FET sensors, we have experimentally extracted...
We have successfully experimentally integrated graphene interconnects with commercial 0.25 ??m technology CMOS ring oscillator circuit using conventional fabrication techniques, and demonstrated high speed on-chip graphene interconnects that operates above 1 GHz.
We have developed a curvable photovoltaic monolithic retinal implant that requires no electrical power or data connection. The implant consists of a two-dimensional network of miniature silicon solar cells that directly stimulate the retina when illuminated by a goggle system. A MEMS process isolates adjacent pixels and makes the arrays curvable allowing them to conform to the shape of the retina.
We report on field-effect transistors based on single-crystalline ZnO nanowires with a diameter of about 50 nm grown by wet-chemical synthesis. The as-grown nanowires have a large conductivity that makes it difficult to control the drain current with the gate field, but the conductivity is greatly reduced by a post-growth anneal at 600??C. Using a solution-processed organic gate dielectric with a...
We have fabricated FETs and CMOS inverters with 20 nm contact holes patterned using self-assembled diblock copolymer. Alignment of the self-assembled contact holes to the MOSFET source and drain is achieved with a guiding layer. The self-assembly process is integrated with an existing CMOS process flow using conventional tools on a full wafer level. This is the first demonstration of functional circuits...
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