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On behalf of the entire IEDM committee, I would like to welcome you to the 2009 IEEE International Electron Devices Meeting to be held December 7–9, 2009 in Baltimore, MD. The IEDM continues to be the world's premier venue for presenting the latest breakthroughs and the broadest and best technical information in electronic device technologies. This year we have a strong collection of both contributed...
This paper discusses the importance of discipline and risk management in the design of new high performance microprocessors in advanced technologies. Innovation is very important in these designs but the design costs have to be assessed and the risks managed.
This paper presents technology and economic challenges posed by 22 nm CMOS and beyond. They can be addressed by advances in design technology, methodology, validation, and testing, to continue to enjoy the benefits of CMOS scaling in the future, as we have over the past decades.
High-k, metal gate devices and furthermore multi-gate FETs (MuGFETs) are considered as promising solution for scaling down to 32 nm, 22 nm and 16 nm overcoming the limitations of conventional planar bulk. Especially analog, mixed-signal and RF device and circuit performance is affected by these revolutionary changes in technology. This paper discusses different examples for novel, technology related...
Large scale integration with advanced CMOS technologies has been reducing cost, but maintaining chip dependability is becoming more and more difficult. This is due to increasing complexity of system design and increasing uncertainty of signal timing and level. Chip dependability can be realized at low cost and maintain high efficiency by combining technologies of (A) ??Never produce defects?? during...
The economic and technological challenges of process development are threatening the timely availability of advanced nodes. Meanwhile design and product organizations are demanding the continued delivery of Moore's law density scaling to justify node migration. Balancing the requirements of design with the capabilities and physical limitations of advanced processes will require capitalizing on opportunities...
This paper presents challenges in the advanced process technologies, and the need to adopt a new collaboration model between the designer and the foundry.
We have demonstrated the injection, modulation and detection of pure spin diffusion current in silicon in a lateral transport geometry compatible with existing device design, fabrication and scaling. This approach injects spin-polarized electrons near the silicon conduction band edge with near unity conversion efficiency and low bias voltages (~ 2 eV) compatible with CMOS technology.
High-k materials, such as HfO2 and Al2O3, are known to have dielectric relaxation effect (i.e. slow polarization). It is reported for the first time in this work that Al2O3, used as a blocking layer of MANOS NAND flash memory cells, causes modulation of channel current through its dielectric relaxation, resulting in severe transient threshold voltage shift as much as ~0.8 V. This Vth drift cannot...
We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 μm2. This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated...
Record area size of 0.039 μm2 for a functional 6T-SRAM cell has been successfully achieved with a novel Nano Injection Lithography (NIL) technique and dynamic Vdd regulator (DVR). The NIL technique is not only maskless for minimizing entry cost but also photoresist free to greatly enhance pattern resolution, down to 2 nm 3-sigma line width roughness, and without significant proximity effect. Devices...
In this paper, we describe a gate-first self-aligned MBE InGaN regrowth methodology for fabricating N-polar GaNbased MIS-HEMTs which exhibit ultra-low contact resistances of 23 Ω-μm, which is comparable to the lower band-gap technologies. These devices, not only show state-ofthe-art fT.-LG product values of 16.8 GHz-μm for 130 nm gatelength for GaN, but also show exceptional performance at low supply...
Vertical In0.53Ga0.47As tunnel field effect transistors (TFETs) with 100nm channel length and high-k/metal gate stack are demonstrated with high Ion/Ioff ratio (>104). At VDS = 0.75V, a record on-current of 20??A/??m is achieved due to higher tunneling rate in narrow tunnel gap In0.53Ga0.47As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming...
We report the DC and switching performance of a normally-off 5 A/1100 V GaN-on-Si device. The device had a breakdown field of 95 V/??m and a VB2/Ron,sp of 272 MW/cm2. A 360 V/180 W boost converter was operated at 200 KHz, with an efficiency >92%. Respectively, these values are the highest for a normally-off GaN-on-Si device.
We report high performance (100) and (110) oriented single-grain thin-film-transistors (SG-TFTs) fabricated below 600??C without any seed substrate. The orientation has been contolled by ??-Czochralski process with the excimer laser. Field-effect mobility of n-channel transistor is 998cm2/Vs for (100) SG-TFTs and 811cm2/Vs for (110) SG-TFTs. Field-effect mobility of p-channel transistor is 292cm2/Vs...
A novel five-mask low temperature polycrystalline silicon (LTPS) complementary metal oxide semiconductor (CMOS) structure was verified by manufacturing Thin Film Transistor (TFT) test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed without additional photo mask steps to solve the...
First results of 100 V, novel Trench Super Junction HVTFTs fully compatible to the LTPS technology are presented. They exhibit ON/OFF current ratio of more than 107 with sub-threshold swing of 0.75 V/decade and specific resistance (Rsp) of 40 ??mm2.The influence of geometric parameters on both unipolar and bipolar devices is analysed.
We investigate the role of the 0.5 eV traps in determining GaN HEMT degradation by means of DC and rf testing, and 2D numerical simulation. We demonstrate that generation of deep levels, having an activation energy of 0.5 eV, is responsible for the degradation observed during rf aging; we show that the occurrence of trap-induced degradation depends on rf driving conditions. We also show that degradation...
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