The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A 1 GHz Low Noise Amplifier and Mixer combination has been integrated in a standard 1??m CMOS process. The circuit is matched to 50?? at the input, and drives a 50?? load. Overall conversion gain is 22 dB, noise figure is 3.5 dB, and the IIP3 of the combination is +12 dBm. The fully balanced circuit drains 8 mA from 3V.
We present contactless signal measurements inside a 100 MHz Intel Pentium micro processor carried out with a scanning force microscope (SFM) tester. This new test technique offers voltage contrast within passivated integrated circuits with nanometer spatial resolution and gigahertz measurement bandwidth. Contactless device internal waveform measurements up to 320 MHz on the clock line of a passivated...
A phase detector for timing recovery phase locked loops with an accuracy better than 0.5 % for input frequencies up to 100 MHz is presented. The core of the phase detector consists of two modified Gilbert cells combined so that the offset in their output current is cancelled. This core is expanded with logic circuitry at the input to make the phase detector suitable for timing recovery applications...
A new smart power switch for industrial, automotive and computer applications developed in BCD (Bipolar, CMOS, DMOS) technology is described. It consists of an on-chip 70 mΩ power DMOS transistor connected in high side configuration and its driver makes the device virtually indestructible and suitable to drive any kind of load with an output current of 2.5 A. If the load is inductive, an internal...
A BiCMOS integrated gate-drive (IGD) ASIC has been implemented in a 18V, 3-??m BiCMOS technology for IGBT based intelligent power modules (IPM). It features various monitoring and control functions such as linear dv/dt feedback and master-slave control of IGBTs, and is capable of delivering 16-18A peak current to high capacitive loads. The gate-drive ASIC has also been tested in a high voltage half-bridge...
The term EMC (Electromagnetic Compatibility) includes, as generally might be known, all actions intended to eliminate electromagnetic interference in electronic systems. Challenges faced in the microelectronic area include growing systems complexity, higher operating speed, denser design at all levels of integration (chip, printed circuit board, MCM and system).
The hot-carrier induced degradation of the transient circuit performance in cascaded CMOS digital circuit structures is investigated and the degradation of tapered (scaled) inverter chains is modeled. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output...
An 8-bit acquisition interface for multistandard video applications is presented. A clamp, AGC, 10-pole analog filter bank, 8bit-ADC and synchronization signal extractor have been integrated together in this mixed mode IC. Low noise design and improved filter cells were key issues in achieving full integration of the functions in a 13-GHz BiCMOS process for a power dissipation less than 500mW under...
Today's technologies exhibit excellent performance for specific applications, e.g. CMOS for VLSI circuits, bipolar for precision analog signal processing, and GaAs for very high speed circuits. In future telecommunication products the monolithic integration of many of these functions will be mandatory. An improved CMOS-technology on silicon-on-insulator (SOI) substrates which allows the realization...
A second-order current-mode bandpass filter employing current controlled conveyors and implemented in BICMOS technology is presented. Both high center frequency f0 and high Q value have been achieved with low power consumption. A 85MHz IF stage for a mobile communication terminal, based on the cascade of two former cells, has been realized. Measurements results are obtained in good accordance with...
In this paper, we present a CMOS operational amplifier with high DC-gain and high output swing despite a low supply voltage. This Op Amp uses a new technique called the TransComposit. The Op Amp has been manufactured in standard 0.5-??m CMOS technology. Using this technique the Op Amp can operate at a 3V supply voltage at a 67db DC-gain and 116MHz unity gain frequency with 25-pF load capacitance.
A low-power Infrared communications transceiver is presented. It is used in an integrated label data communications environment for retail business applications (Super markets). The circuit features a novel active shunt circuit [1] and a novel AGC structure [2]. Low power consumption is the key criterion of this design. It operates under 2.1 V of power supply voltage, consuming less than 60 ??A and...
This paper compares two realisations of a self-timed ring arithmetic operator for division and square-root extraction. The operator receives its inputs and delivers its outputs in conventional binary notations. The first circuit design uses Differential Cascode Voltage Switch Logic. The second adds True Single Phase Clock latches in the ring. It is shown that this addition both reduces the minimum...
A new offset-trimming bit-line sensing scheme is described which is suitable for Gigabit-scale DRAM's. This sensing scheme can suppress the sensitivity degradation caused by the large electrical parameter variation of deep submicron transistors. The effective offset voltage dependence on trimming time is analyzed and verified with simulation results. As compared with a conventional direct sensing...
This paper describes the design and measurement results of an octal mixed analog-digital signal processor used for the Alcatel subscriber line circuit. The device includes 8 analog front ends serving 8 subscriber line terminals and DSP functions such as decimation, interpolation and digital sigma-delta modulation which are included as independent datapaths. The D/A conversion of the 12/16 kHz metering...
A 3rd order active lowpass filter for antialiasing and smoothing applications, which is based on distributed RC elements, is presented together with a procedure for optimum design of this type of filter. When compared to filters using lumped resistors and capacitors, distributed filters offer steeper stopband roll-off, higher crosstalk insensitivity, and require smaller chip area.
This paper describes how the "S3" standard-cell library helps optimising the speed of circuits; and reduce their power dissipation and the silicon area they occupy. The "S3" standard-cell library is designed and used with automated compilers to produce blocks layout with a performance close to one of layouts produced by hand. The cells are interconnected by rows and overall layout...
Frequently problems of VLSI optimal design are formulated as the optimizational models of Boolean programming, characterized by NP-completeness. We suggest a probability approach to algorithmization of such problems, using some aspects of quick "greedy" algorithms and extending their possibilities.
In this paper a 3V 2nd order lowpass continuous-time filter is presented. The filter is based on a highly linear pseudo-differential transconductor. The input common-mode signal is cancelled at the transconductor level using a feed-forward path. The output common-mode voltage is controlled at the filter level using lossy-integrators. A prototype cell has been realized in 1.2??BiCMOS technology. The...
A new bit/frame synchronizer with optimum clock extractor and elastic serial-to-parallel (S/P) converter is presented. The circuit selects the suitable clock from equally phased multiple clocks generated by a PLL. The elastic S/P converter not only expands the bits but also recovers the frame synchronization. By our compact circuit implementation, the total hardware amount is greatly reduced. The...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.