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A CMOS receiver for optical wireless communication is presented. A stable feedback transimpedance amplifier (TIA) is designed adopting a current-mode amplifier as its feedforward gain element. A band-pass limiting amplifier is employed to boost the outputs of the receiver front-end. Implemented in a 0.35 um CMOS, the optical wireless receiver achieves a maximum transimpedance gain of 95.9 dBΩ. The...
This paper presents a wide intermediate-frequency (IF) bandwidth down-conversion double-balanced Gilbert-cell mixer design in a 0.13-μm CMOS process. The load stage of the mixer is implemented by an LC tank with switched capacitors to complete three selectable sub-bands to cover the desired wide IF band. Both the RF and LO ports are integrated with Marchand baluns for single-phase input consideration...
This work investigates device performances of an AlGaAs/InGaAs metal-oxide-semiconductor pseudomorphic high electron mobility transistor (MOS-pHEMT) by using ozone water oxidation treatment. Experiment results indicate that the studied MOS-pHEMT has demonstrated superior device characteristics as compared to a conventional pHEMT without oxidation treatment on the same epitaxial structure. The studied...
This paper presents a high-throughput deblocking filter accelerator which can process one macro block (MB) within 48 cycles for H.264/AVC/SVC. This innovation is achieved by considering both luminance and chrominance data together in arranging the filtering schedule. Cooperating with the filtering schedule, the proposed quadruple-filter-based architecture can simultaneously execute filtering of four...
In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the...
Silicon-controlled rectifier (SCR) has been reported with the good electrostatic discharge (ESD) robustness under the lower parasitic capacitance among ESD devices in CMOS technology. To correctly predict the performances of SCR-based ESD-protected RF circuit, it is essential for RF circuit design with accurate model of SCR device. The small-signal model of SCR in RF frequency band is proposed in...
This paper presents a non-conventional CMOS device, which is composed of an nMOSFET and a tunneling field effect transistor (TFET) for driver and load. Based on the measurement data of TFET device published, we have for the first time drawn the Q line of the new designed CMOS compared with the conventional CMOS to verify its feasibility. The static power consumption of it can be optimized and reduced...
Here we present the design and implementation of a 130-MHz on-chip reference oscillator in a 0.18-μm 1-ploy 6-metal digital CMOS process. To compensate for the influences on the oscillation frequency by process, supply voltage and temperature (PVT) variations, the oscillator uses a bias adjustment technique without BJT devices, on-chip inductors or external components. Measurements of 8 samples in...
This study proposes an approach to estimate parasitic capacitance shift under mechanical stress. The silicon-on-insulator n-/p-metal-oxide-semiconductor field-effect transistors (MOSFETs) and CMOS ring oscillators (ROs) were fabricated side by side in this study. External compressive stresses were applied on a <;110> strained channel of n-/p-MOSFETs and ROs in longitudinal and transverse configurations...
A location awareness system uses a wireless remote sensing technology to provide users with immediate addressing services. The application of radio frequency identification (RFID) technology to navigate a location is provided in this paper. The proposed UHF RFID location system, based on a known location of the reference tags by applying the cosine theorem to calculus more location information, can...
In this paper, two non-ideal effects, carrier frequency offset (CFO) and IQ imbalance, are jointly compensated for an orthogonal frequency division multiplexing (OFDM) system. Based on the two identical sequences in the preamble, a LS-based method is proposed to estimate both CFO and IQ imbalance. This method has much lower complexity than the state-of-art expectation-maximization (EM) approach. Simulation...
In this paper, for the first time, we demonstrate the radio frequency (RF) performance of a junctionless vertical MOSFET (JLVMOS). According to the numerical simulation results, the JLVMOS can obtain higher gm, lower gd, in comparison to a junctionless planar SOI MOSFET. This because the vertical double-gate (DG) scheme truly helps to increase the gate controllability over the channel region, resulting...
This paper presents a direct digital algorithm for digital PID-controlled switched-mode power supplies (SMPS). The crossover frequency and phase margin of the closed-loop system can be set using the proposed approach. The algorithm determines the PID controller parameters, and in the proposed procedure is clearly. The algorithm also takes into account the integral gain to prevent limit-cycle oscillation...
Hafnium-based dielectrics have been extensively investigated as a possible replacement for SiO2. Anhydrous Hf/Zr mixed-metal nitrate precursor HfxZr1-x(NO3)4 (HZN) was successfully synthesized and hafnium zirconate (HfxZr1-O2) thin films were prepared by the chemical vapor deposition (CVD) technique from this precursor. The basal dielectric properties of HfxZr1-O2 films were studied, and C-V curves...
Highly semi-polar (101̅3) oriented and fine structural AlN films were successfully prepared on silicon substrate by rf magnetron sputtering in this research. The dependence of the nitrogen concentrations and the material characteristics of the films (crystalline structure and micro morphology) were investigated. The crystalline structure of the films was determined by X-ray diffraction (XRD) and the...
In this paper, we present an interface for connecting the master/slave ports of hardware modeled in SystemC to a QEMU and SystemC based virtual platform. The virtual platform uses QEMU as the instruction-accurate instruction set simulator (IA-ISS) and is capable of running a full-fledged operating system such as Linux. The proposed interface enables the hardware modeled in SystemC to access hardware...
Dual-core platforms are growing as a new industry trend as platforms with only one core cannot easily perform the diverse functions in current embedded system applications, such as smart phones. We establish an easy-to-use co-simulation dual-core virtual platform to validate the functionality of hardware and software jointly. In our platform, the hardware components are implemented by SystemC, and...
Silicon nitride gate capping by contact etch-stop layer (CESL) was used in this study to induce high and low tensile and compressive stresses on 50-, 70-, and 90-nm thick silicon-oninsulator (SOI) n-/p-MOSFETs. The devices with thicker SOI show a higher interface state, particularly the highly strained devices, although they exhibit higher mobility. The carrier mobilities of different CESL configurations...
Three dimension (3D) graphics applications have been widely used in handheld devices which are an inevitable tendency in the future. In this paper, we model a complex 3D graphics SoC hardware by using SystemC and run some testbenches on this platform. For speeding up the simulation time, we adopt Transaction Level Model (TLM) and implement two type of rendering approaches, tile-based and triangle-based,...
In this paper, an efficient VLSI architecture for convolutional code decoding algorithm is presented. This algorithm locates all erroneous segments of the received sequence and then applies our proposed decoder to these segments only. Besides, the clock-gating technique is used to disable the non-working registers of our design to further reduce the power consumption efficiently with no bit error...
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