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It has been established in prior research that significant power can be saved by dynamically trading off the performance of individual RF modules for power consumption across changing channel conditions. It has also been shown that the control law that reconfigures the RF front end must take into account the process corners from which the RF devices are selected in order to trade off performance for...
A multi-phase technique for speeding up the measurement of delays via sub-sampling is presented. Measurement of delays using the sub-sampling approach leads to a very simple system implementation, and also provides the opportunity of trading off between bandwidth and accuracy. Such a scheme becomes extremely attractive for deep sub-micron processes due to its highly-digital nature and the ability...
Super harmonic division at low power consumption in unilaterally injection locked current controlled ring oscillator system has been explored. Frequency divider for PLL output stage divides a 2.0GHz PLL clock by 2 while consuming just 68uW from a 1.2V power supply. Current Controlled Ring oscillator has been made using single ended inverter stage in 65nm cmos. Two new architectures are proposed to...
With the extensive use of clock-gating in modern microprocessors to reduce the power consumption of the chip, it is imperative to analyze the effect of clock-gating on the Power Distribution Network (PDN) and how it affects the voltage drop across the grid. This paper presents a methodology to generate a set of synthetic gating patterns given a power grid, information about how the grid is loaded...
Near-Threshold Voltage (NTV) design brings the promise of an order of magnitude improvement in energy efficiency over the current generation of silicon systems. This paper describes circuit techniques and benefits of NTV design as demonstrated by Intel's Near Threshold Voltage IA-32 Processor and discusses key technologies which are absolutely essential for harnessing true potential of NTV towards...
This paper explains a circuit architecture to minimize the impact of IRO (Input Referred Offset) in Differential amplifier based Receivers. Such receivers are used on high speed interfaces, like DDRs and LVDS, as they provide better timing and ensure proper detection of small swing signals. However the mismatch between the differential input arms causes IRO which in turn causes duty cycle distortion...
This paper presents a novel process, voltage and temperature (PVT) invariant voltage reference generator using subthreshold MOSFETS. The proposed circuit uses weighted average of PTAT and CTAT voltages at zero temperature co-efficient point. The proposed circuit has been designed and optimized in 180nm mixed-mode CMOS technology. Simulation results show that the output voltage of the proposed voltage...
In many applications, image and video signals are corrupted by impulse noise during acquisition or transmission. Hence there is a need for an efficient and consumer friendly impulse noise removal technique. In this paper, an efficient low cost VLSI architecture for the edge preserving impulse noise removal technique has been proposed. The architecture comprises of two line buffers, register banks,...
Deep sub micron designs are susceptible to huge variations, justifying the in-situ optimization of power consumption in SoCs and IPs. It is essential to scale voltage to the lowest possible value to get maximum power saving while ensuring correct operation. Accurate estimation of error rates is required to use recovery driven DVFS techniques such as slack optimization [1], [2]. Due to extra logic...
The HDMI Transmitter's output driver capable of datarate 3.4Gbps/channel is designed in 40nm technology using the single-ended structure instead of the conventional Differential Current Mode Logic buffer. There is 40% gain in area because of the proposed structure. The power consumption of the implemented HDMI Transmitter Electrical Physical layer is 80mw@10.2Gbps (3.4Gbps/Ch) as seen on silicon.
For a combinational circuit, area-complexity is a measure that estimates the logic area of the circuit without mapping to logic gates. Several measures like literal count, number of primary input/outputs, etc. have been used in the past as area-complexity metrics. In this paper, we propose a novel area-complexity measure using the theory of Boolean difference and Taylor expansion for Boolean functions...
Low power design and verification at the Electronic System Level (ESL) have recently emerged as a challenging research field. This work presents a reliable solution to add such capabilities to Transaction-Level virtual prototypes composed of black-box hardware Intellectual Properties (IPs). This solution relies on a wrapper-based approach in which power intent specification and verification are added...
This paper presents a two-path design of quadrature band-pass modulators and discusses the architectural level implementation issues for power reduction. The methodology uses an architecture which locks IF frequencies to the sampling frequency. The basic delay based solution is converted into integrator based solution for the implementation. Robustness of the structure against the mismatch...
Drastic increase in design complexity along with the emergence of new failure mechanisms in the nanometer regime has led to significant increase in the complexity of verification, validation, and debug of integrated circuits. In spite of extensive efforts, it is not always possible to detect all the functional errors and electrical faults during pre-silicon validation. Post-silicon validation is used...
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