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This paper presents a 12-channel, low-power, high efficiency neural signal acquisition front-end for local field potential and action potential signals recording. The proposed neural front-end integrates low noise instrumentation amplifiers, low-power filter stages with configurable gain and cut-off frequencies, a successive approximation register (SAR) ADC, and a realtime compressed sensing processing...
Although the trend of technology scaling is sought to realize higher performance computer systems, it also results in Integrated Circuits (ICs) suffering from increasing Process, Voltage, and Temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guardband is not...
Lattice reduction (LR) is a preprocessing technique for multiple-input multiple-output (MIMO) symbol detection to achieve better bit error-rate (BER) performance. In this paper, we propose a customized homogeneous multiprocessor for LR. Each individual core is based on transport triggered architecture (TTA). We propose a few modifications of the popular LR algorithm, Lenstra-Lenstra-Lovász (LLL) for...
A novel stability condition is developed in this paper. It is both necessary and sufficient, which ensures that optimal design cannot be excluded from the admissible solutions. Compared to other necessary and sufficient stability conditions, the proposed one can be expressed as a quadratic constraint in terms of denominator coefficients, which facilitates its combination with other widely used IIR...
We study a class of composite digital filters, each has a dominating FIR component of order N and an extremely simple IIR component of order r with r-C N that are connected in parallel. We show that a constrained optimization setting known as convex-concave procedure (CCP) is naturally suited for the design of stable composite filters where the FIR and IIR components are jointly optimized in frequency-weighted...
In this paper we investigate the hardware implementation of the subspace marginalization with interference suppression (SUMIS) detector using high-level synthesis (HLS). SUMIS is a promising detection approach for multiple-input multiple-output (MIMO) systems, due to its fixed computational complexity and well-defined tradeoff between complexity and performance. Based on a SystemC implementation,...
In this work we consider the implementation of nondeterministic finite automata in autoassociative memory, and demonstrate mapping and operating such automata in an associative content-addressable/Willshaw-type memory circuit presented in a companion paper. This topic is relevant in the broader scope of in-memory computing, and offers a simple, flexible, and computationally efficient way of implementing...
In this paper, we present an overview of recent advances in multidimensional (MD) systems and signal processing. We focus on topics closely related to the four papers selected into the special session of “recent advances in multidimensional systems and signal processing” at ISCAS 2015. The paper starts with an overview of the theory of MD IIR digital filters and its applications ranging from image/videos...
This article describes a laboratory component of a course in fractional calculus for undergraduates. It incorporates theoretical, experimental, and numerical analyses of the fractional harmonic oscillator. Three independent approaches were taken to obtain solutions to the fractional harmonic oscillator excited by a step function: 1) a power series expansion of the Riemann-Liouville form, 2) a circuit...
We propose a very fast fault simulation method which is based on exact parallel critical path tracing developed for combinational circuits. To convert the sequential problem of fault simulation into the combinational one we introduce into the circuit a set of MISRs to improve the circuit's observability. The role of these MISRs is to monitor signals on the global feedback loops, and on selected fan-out...
This paper presents a two-regulator power management system for ultra-low power energy harvesting applications. The system consists of an RF-to-DC converter, an LDO and an SC regulator that are connected in parallel operating alternately, and a voltage detector for choosing the operation mode. The system produces a stable 1.2-V output power supply, using a wide range of input DC voltages (0.7…2 V)...
Tunnel Field Effect Transistor (TFET) based on Band-to-Band tunneling mechanism is a revolutionary device technology that has a very strong potential to break the thermodynamic barrier of conventional FETs and provide a very steep subthreshold slope. However, TFETs in general suffer from low on-state current (ION). We propose a new TFET structure to increase the drain-to-source current of the tunneling...
This paper introduces a modeling framework to predict the efficiency scaling of switched-capacitor (SC) dc-dc converters under power density constraints. A reference power density metric is introduced under which SC converters are integrated directly on silicon using the available decoupling capacitance without increasing the chip footprint. An analytical model is then employed to predict the scaled...
In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive...
Machine vision applications involving the assistance of robots for scene mapping or object classification encounter issues when faced with smooth transparent surfaces, such as glass. Specular reflection from such surfaces saturate the image sensor pixels, restricting their vision of objects beyond the surface. The problem is aggravated by the movement of the robot, making traditional approaches unfeasible...
In this paper is presented a High Dynamic Range (HDR) extension technique that applies to an imager without modifying any of its other specifications (as speed, noise floor or pixel scheme). The technique relies on the division of the focal plane into blocks that are able to choose the integration time from a set of eleven exposures, reaching +60db extension compared to a standard CMOS imager. The...
Power systems subjected to large disturbances may become transiently unstable, which can lead to uncontrolled system separation and cascading outages. An important goal of developing the smart grids is to maintain high-level system stability. Controlled islanding is a corrective measure that can efficiently attenuate the detrimental impact of large disturbances by splitting the system into self-healing...
Physical Unclonable Functions (PUF) is an emerging design technology for secure hardware. It exploits the physical manufacturing variations of silicon ICs to generate a unique signature for each chip. A Ring Oscillator (RO) based PUF is a promising solution for the authentication of FPGA devices. However; this technique has not yet been widely adopted due to its large area costs and the lack of platform-independent...
In this paper, a methodology towards a hardware/software implementation of an Elliptic Curve Diffie Hellman (ECDH) scheme is proposed in an effort to overcome the design problems of Elliptic Curve Cryptography (ECC) systems stemming from the highly constrained embedded system hardware and software environment (restricted RAM, storage and processing power). To achieve that, instead of the excessively...
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