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The average smart phone user picks up the device 1,500 times a week. Wireless communication appears to be taking over our lives but it also presents interesting challenges to RF designers. This paper contends that the mobile terminal will emerge as a central command post for most of our daily affairs and will therefore sustain an increasingly heavier load in terms of speed, power dissipation, and...
This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operation, and a WRITE protocol to minimize the current at each row and column lines. The presented circuit has been designed in 180nm standard CMOS technology...
New computer memory hierarchy based on spintronics is proposed for low-power electronics that will evolve in two steps from the current volatile system. At first, memories for internal states and pipeline registers and cache memories etc. are made nonvolatile by using spintronics. Then, computers can be made totally nonvolatile by additionally adopting spintronics-based logic-in-memory architecture...
Discovery of memristor opened a new era of the research on universal memory thanks to many attractive properties demonstrated by this emerging device. In this paper, we switch our research focus to neuromorphic computing, which, same as memory technology, significantly benefits from the technical advances of memristor. Particularly, we present the implementation of cortical processor augmented with...
Emerging nonvolatile memory (NVM) technology i.e., phase-change memory (PCM) has been commonly employed as a drop-in replacement for either DRAM or Flash. However, the inherent nature of PCM technology does not align perfectly with either applications in terms of cost-per-bit, performance, power, endurance or retention. The missing killer applications for PCM have slowed down the technology development...
Application developers are now turning to field-programmable gate array (FPGA) devices for solutions of small to medium volume due to its post-fabrication flexibility. Unfortunately, the existing upfront intellectual property (IP) licensing model for FPGA based third-party IP cores is economically unattractive. The IP bitstreams in transaction are also vulnerable to cloning, misappropriation and reverse...
Proof carrying hardware intellectual property (PCHIP) introduces a new framework in which a hardware (semiconductor) Intellectual Property (IP) is accompanied by formal proofs of certain security-related properties, ensuring that the acquired IP is trustworthy and free from hardware Trojans. In the PCHIP framework, conversion of the design from a hardware description language (HDL) to a formal representation...
The modern secure systems are designed to require ultra-low power secure solutions due to their energy constraints. Compared to the classical cryptography approaches, the physical unclonable functions (PUFs) have emerged as a novel security primitive with the property of low power/energy, small area, and high speed. Among the family of PUFs, delay-based PUF takes advantage of the process variation...
Modular design of a system-on-chip (SoC) exposes intellectual property (IP) and SoC assets to attacks in test, debug, and functional modes. We enhance the SoC Design-for-Test (DfT) infrastructure with security countermeasures to thwart these attacks. We first secure IP and SoC assets from attacks in test and debug modes, then reuse the DfT infrastructure to detect attacks in functional mode.
Integrated circuit chips fabricated using nano-scale CMOS technologies will be prone to errors caused by fluctuations in threshold voltage, supply voltage, electromigration, random dopant fluctuations, aging, timing errors and soft errors. Design of nano-scale failure-resistant systems has drawn significant interest in past few years. One common approach to reducing errors is the use of triple modular...
Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency in technology-scaled and low-power digital systems. Such strategy is suitable for error-tolerant applications involving perceptive or statistical outputs. This paper presents a novel architecture of an Inexact Speculative Adder with optimized hardware efficiency and advanced compensation technique...
As the size of semiconductor devices has decreased, reliability degradation caused by soft-errors has become one of the greatest issues in VLSI circuit design. In this paper, we propose a method to synthesize soft-error tolerant application-specific datapaths via high-level synthesis. Our method is based on a concurrent error detection and a retry mechanism for error detection and error correction...
Efficient modular adders and subtractors for arbitrary moduli are key booster of computational speed for high-cardinality Residue Number Systems as they rely on arbitrary moduli set to expand the dynamic range. This paper proposes a new unified modular adder/subtractor that possesses a regular structure for any modulus. Compared to the latest modular adder/subtractor, which works for modulus in the...
In his paper a method of seizure detection has been proposed based on the Discrete Wavelet Transform (DWT) analysis of the dominant Intrinsic mode function(IMF) resulting from the Empirical Mode Decomposition(EMD) of the EEG signals. Considering the normalized energy, Fourier spectrum and cross-correlation coefficient analysis, only the 4th Level DWT coefficients of the dominant IMF is found reasonable...
This paper proposes a dynamic nonlinear autoregressive model based algorithm for gene regulatory networks (GRNs) identification with biological stage change detection using the L1-regularization. This allows subtle variations in the same state to be penalized and prominent changes across adjacent states to be captured. Furthermore, by assuming local-stationarity within each detected biological state,...
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