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Current trends in Nan electro magnetics - a new field of research synthesizing classical radio physics and electrodynamics with quantum theory of solids, physical kinetics, quantum chemistry, computational mathematics - are analyzed with the focus on applications in the terahertz frequency range. The analysis is exemplified by the discussion of the THz response peculiarities of carbon nanostructures...
Dynamic flip-flop conversion (DFFC) is a time borrowing method which converts the critical flip-flops into transparent latches to allow timing slacks pass between pipeline stages of given circuits. However, our previous DFFC methods [13] [14] suffer from false error prediction. It means even when there is no setup time violation, our previous method incorrectly issues timing error. In this paper we...
Analytical methods for estimating on-chip network performance can be very useful to accelerate and simplify the design process of Networks on Chip. However, in order to increase the confidence in these approaches it is fundamental to perform systematic studies that assess their potential. We present a methodical investigation on the tightness between analytical end-to-end delay bounds and worst-case...
Halving methods have been proposed for parallel implementation of ECC primitives on multicore processors. In hardware, they can also provide protection against some side channel attacks (thanks to parallel independent operations). But they require affine coordinates for curve points and costly inversions. We propose a new combined multiplication-inversion unit for binary field extensions and halving...
The results of the theoretical study of interband THz transitions in narrow-gap carbon nanotubes and graphene nanoribbons are reported. We consider dipole transitions across magnetically-induced gaps in armchair nanotubes, curvature-induced gaps in quasi-metallic nanotubes and edge-effect induced gaps in armchair nanoribbons. A giant enhancement of the transition matrix elements is discovered for...
Most die area of today's systems-on-chips is occupied by memories. Hence, a significant proportion of total power is spent on memory systems. Moreover, since processing elements have to be fed with instructions and data from memories, memory plays a key role for system's performance. As a result, memories are a critical part of future embedded systems. Continuing CMOS scaling leads to manufacturing...
Standard cell design and memory design need to be optimized for sub-threshold operation. It is interesting to revisit digital block architectures when implemented using these sub-threshold basic bricks. Out of many possible architectures for the same logic function (i.e. Multiplier), it turns out that there are optimal sub-threshold architectures.
Nowadays critical integrated circuits are facing the threat of being invaded, counterfeited and pirated by various malicious adversaries. The topic of Hardware Trojan has gained increasing attention in the past decade. Particularly, a plenty of countermeasure approaches have been investigated to obfuscate the design to avoid hostile circuit insertion during the manufacturing stage. Inspired by the...
The growing complexity of modern automotive embedded systems requires new techniques for model-based design that take into consideration both software and hardware constraints, and enable verification at early stages of development. In this context, EAST-ADL has been developed as a domain-specific language dedicated to modeling functional-, software-, and hardware-architecture of automotive systems...
In the field of safety-critical applications, the industry has seen a dramatic increase in system integration and complexity for on-chip solutions, and this provides new challenges in gaining deep testability access within such products. IC developers have responded to this challenge by creating sophisticated on-chip trace/test/debug modules to facilitate real-time access to application programs'...
The technology advancements in semiconductor process have led to rapid progress in design and fabrication of multiple-input Nano-electro-mechanical relays/switches (NEM relays/NEMS). This work explores the design space of implementing image processing algorithms using a hybrid multiple-input NEMS -- CMOS architecture. Different from the existing the approaches of building logic gates (e.g. INV, AND,...
Hap tic and robotic interfaces are recently gaining momentum to be pervasively integrated in modern everyday life. In fact, they can be employed in several different fields, ranging from manipulation of small and dangerous objects to rehabilitation, assistive and service technologies, and are also integrated in mission critical systems. Modern research is rapidly shifting to investigate novel and...
Among all means to attack a security dedicated circuit, fault injection by means of laser illumination is a very efficient one. The laser beam creates electrons/holes pairs along its way through silicon. Collection of these charges creates a transient current and thus may induce a fault in the circuit. Nevertheless the collection efficiency depends on various parameters including the technology used...
Nowadays, electronics systems design is a complex process. A design-and-reuse model has been adopted, and the vast majority of designers integrates third party intellectual property (IP) cores in their design in order to reduce time to market. Due to their immaterial form and high market value, IP cores are exposed to threats such as cloning and illegal copying. In order to fight these threats, we...
Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. Targeting to increase performance, in this work, we focus on optimizing the design of the modulo 2n ± 1 Add-Multiply (AM) operation. The proposed modulo 2n ± 1 fused AM units incorporate an initial row of Half Adders which carry out the requested addition of two specified operands resulting to an intermediate...
In this paper, we propose a new sub-threshold 9T-Static Random Access Memory (SRAM) cell in 14 nm Fin FET technology by which the access time of the memory cell is improved by at least 30 percent compared to the standard 8T-SRAM cell. Furthermore, the leakage current of the proposed SRAM cell is reduced by an assisting circuit. Simulation results show that the leakage of the proposed cell is reduced...
This paper presents a novel diagnosis and logic debugging method for gate-level arithmetic circuits. It detects logic bugs in a synthesized circuit caused by using a wrong gate ("gate replacement" error), which change the functionality of the circuit. The method is based on modeling the circuit in an algebraic domain and computing its algebraic "signature". The location and type...
Efficient mapping of DAGs on heterogeneous multicore platforms is a key component for modern embedded applications. An approach based on the Benders decomposition principle that uses a heuristic pre-solver and Integer Linear and Constraint Programming methods to find proven-optimal solutions is introduced. We present multiple cuts generation schemes, that improve the performance of the solution process,...
In this paper, we establish a non-trivial duality between tautology and contradiction check to speed up circuit SAT. Tautology check determines if a logic circuit is true in every possible interpretation. Analogously, contradiction check determines if a logic circuit is false in every possible interpretation. A trivial transformation of a (tautology, contradiction) check problem into a (contradiction,...
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