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Although a lot of effort has been spent on verifying arithmetic designs, it is still a problem that has no general robust automated solution. One major challenge is verifying large scale multiplier circuits. For this purpose, we revisit the idea of using functional properties of the multiplication function, which can be expressed by recurrence equations. Then, instead of proving the equivalence of...
Program analysis is a highly active area of research, and the capacity and precision of software analyzers is improving rapidly. We investigate the use of modern software verification tools for formal property checking of hardware given in Verilog at register-transfer level. To this end, we translate RTL Verilog into an equivalent word-level ANSI-C program, according to synthesis semantics. The property...
One application of equivalence checking is to establish correspondence between a high-level, abstract design and a low-level implementation. We propose a new partitioning technique for the case in which the two designs are substantially different and traditional equivalence-point insertion fails. The partitioning is performed in tandem in both models, exploiting the structure present in the high-level...
Although touted as a power and energy-efficient solution for workloads that exhibit data-level parallelism, vector processors were not explored sufficiently from a low power perspective in the past. Therefore, there is a need for explorations of vector computational units from a low power angle. Multimedia workloads that are suitable for vector processing (such as image processing) typically have...
Contemporary digitally controlled delay elements trade off power overheads and delay quantization error. This paper proposes a new delay element that provides a balanced design that yields low power with low delay quantization error. The proposed element has a quasi linear delay characteristic, with uniform delay differences between adjacent code words. The element employs and leverages the advantages...
Due to great advantages of the imprecise computational blocks in implementation of imprecision tolerant applications, a wide range of different imprecise structures as well as some of their new applications are introduced in recent years. However, due to inherent differences between imprecise and precise components, their utilization approaches should also be customized to gain the best performance...
In this paper we propose a detailed placement algorithm targeting detailed rout ability for designs at or smaller than 22nm. The sheer number and complexity of routing design rules at these feature sizes preclude direct incorporation of detailed routing rules into a placement algorithm. However, using the detail routing information to guide the placement can significantly reduce the overall design...
To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous work either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer...
Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor's characteristics in electrical circuits are continuously increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient faults and variability. We present a conservative algorithm to decide if a transient fault leads to erroneous...
Nowadays many application domains require an embedded electronic system for tactile data processing. Our research aims to implement a real time embedded electronic system based on tensorial kernel approach for tactile data processing. Singular value decomposition represents the more computational expensive algorithm for the tensorial kernel approach. This paper presents an assessment of FPGA implementations...
Scalable on-chip communication system such as Network-on-Chip (NoC) is needed to meet the communication demand of large number of SoC (System on Chip) cores. In the NoC router micro-architecture design, arbiter has become increasingly important due to its significant impact on the performance and efficiency of NoC systems. In this paper, we propose an Index-based Round Robin (IRR) arbiter that functions...
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