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Scan-based test is commonly used to increase testability and fault coverage, however, it is also known to be a liability for chip security. Research has shown that intellectual property (IP) or secret keys can be leaked through scan-based attacks. In this paper, we propose a dynamically-obfuscated scan design for protecting IPs against scan-based attacks. By perturbing all test patterns/responses...
The complete presentation was not made available for publication as part of the conference proceedings. Provides a brief professional biography of the presenter.
Adaptive test is a promising direction for reducing the manufacturing test cost. It aims to dynamically adjust the test program on a device-by-device or on a wafer-by-wafer basis. Adjusting the test program could involve eliminating tests, changing test limits, re-ordering tests, etc. The objective is to spend the minimum possible test time per device without sacrificing fault coverage. In this paper,...
This paper introduces a novel fault model, called the dual-cell-aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial...
Small delay defect (SDD) ATPG has been around for a few years now; however, its adoption is not prevalent due to various reasons. (i) Unique detection with SDD ATPG patterns over transition delay fault (TDF) ATPG patterns is often not easy to establish due to the large volume of the former and the insistence on coverage due to the latter. (ii) Lack of a seamless method to target SDD patterns for nodes...
Scan chain faults that affect the scan logic of a design are important to diagnose. However, scan chain faults create large volumes of fail data that make it necessary to terminate the fail data collection process early. An approach to test generation called transparent-scan was shown to have several advantages for diagnosis of scan chain faults over conventional scan-based tests. One of these advantages...
This keynote is a tribute to the late Prof. Mel Breuer, entitled Contributions to CAD and Test. It is organized by Sandeep Gupta. A panel of three prominent speakers gives this keynote. The three speakers are Miron Abramovici, Magdy Abadir and Sridhar Narayanan.
This paper presents a new scan-based at-speed test signal scheme called One Clock Alternated Shift (OCAS) for minimizing the potential impact of the power distribution network PDN impedance variation. The strategy behind this new scheme is to mimic the clock signal of the functional mode as closely as possible. As a case study, we consider the PDN impedance variation that can occur with 3-D ICs, more...
The lack of observability of prototype chips makes post silicon debug extremely difficult and time consuming. Trace based debug techniques can improve the observability by acquiring some internal states at runtime through a dedicated on-chip trace buffer. In this paper, we propose a flip-flop clustering based trace signal selection method, which uses the forward tracing to generate flip-flop clusters...
In recent years early life failures have caused several product recalls in semiconductor and automotive industries associated with a loss of billions of dollars. They can be traced back to various root-causes. In embedded or cyber-physical systems, the interaction with the environment and the behavior of the hardware/software interface are hard to predict, which may lead to unforeseen failures. In...
As the technology of IC manufacturing continually scales down, process variations become more and more crucial than before. To statistically characterize local process variations, the traditional array-based test structure measures threshold voltage (Vt) for a sufficiently large number of devices-under-test (DUTs). However, the array-based test structure requires long time for DUT-by-DUT measurement;...
Spin Transfer Torque Magnatic Random Access Memory (STT-MRAM) has the potential to become a universal memory technology due to its various attractive features such as non-volatility, high density, CMOS compatibility and zero leakage. However, STT-MRAM suffers from high write latency and poor reliability compared to SRAM. This is primarily due to its stochastic nature of switching, which makes it not...
Traditionally, DFT patterns exacerbate dynamic power consumption in large ASICs. At-speed scan and memory tests are sensitive to voltage droop and peak current because the power grid is designed for functional power viruses (maximum workload applications) whose power consumption is much lower than DFT patterns. Our goal in this work is to ensure that the quality of test is not compromised while power...
Integrated Circuits age differently based on their operating conditions. A device that operates under high voltage or temperature stress ages faster. In many safety critical applications, such as in automotive systems, avionics and cyber-physical infrastructure, users would like to know the residual life of its components to ensure timely replacements. This motivates design of a residual-life meter...
With an increasing number of complex cells in today's VLSI designs, intra-gate opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOF) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient...
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