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Polymer film is general used for stress buffer and dielectric film for Wafer Level Chip Scale Package (WLCSP). Chemical resistance and mechanical resistance of polymer films usually get worse after several processes with chemicals or heat. Weak chemical or mechanical resistance will induce polymer film cracking. Polymer cracking further induces humidity penetration into RDL (Re-distribution Layer)...
On the way to full production control, wire bonding equipment requires data-driven condition-based maintenance of the mechanical setup. In this paper, we identify aspects of regular mechanical equipment setups that severely affect bonding quality and equipment health in mass production. We show that mechanical equipment setups lower process stability in aluminum wire bonding. Typical faults in mechanical...
In this paper we will demonstrate a systematic approach for controlling the inputs around a measurement process which has been applied at GLOBALFOUNDRIES Fab 8. The approach covers a wide range of topics which are each individually known but not uniformly applied across the industry. We will discuss the various manufacturing control factors involved around performing a measurement, which can be considered...
Epitaxially grown SiGe and Ge layers on Si <100> substrate have been analyzed by terahertz multispectral reconstructive 3D imaging technique. In particular, 3D images of both samples were generated via a non-contact and no-destructive route and were analyzed by utilizing the terahertz reconstructive imaging algorithm. It was found that the algorithm of “gridding with inverse distance to power...
Manufacturing process control of porous SiOC:H low-k dielectrics is challenging due to their hybrid nature and process damage vulnerability. We discuss advanced optical modeling of various low-k dielectrics that allows one to reflect their material properties and improves accuracy and precision of scatterometry models widely utilized in manufacturing process control. Furthermore, we explore usage...
Electroplating for the sub-50 nm pitch back-end-of-line (BEOL) interconnect metallization has become increasingly challenging mostly because of marginal seed coverage, inadequate plating process and/or chemistry, the limitation of scaling the barrier-liner and seed thickness. In this study we show how inadequate plating due to the marginal seed caused degraded via open yield along the perimeter of...
For metal pitches below 50nm, triple patterning (LELELE) integration is utilized in most advanced technologies to build the Cu interconnect. This integration relies on etch to shrink to the target critical dimension. As a result of high iso-dense bias in conventional etch process, nested serpentine structures formed by different metal colors show massive shorts that limit defect density yield. In...
We discuss utilization of TMU (Total Measurement Uncertainty) analysis based on Mandel Regression for scatterometry model referencing. We demonstrate practical instances where the reference metrology uncertainty seems to exceed that of the scatterometry model which, in turn, forces the TMU analysis into an invalid regime. Knowing that the source of this result is the wrong estimation of the reference...
Power and Advanced BiCMOS technologies use deep trench architecture to reduce capacitance and leakages that are enhanced by high electric fields and high current applications. In this paper, a power and an advanced BiCMOS technology with deep trench architectures used micro Raman spectroscopy to identify non-uniform stress regions in the circuit. Using this information, architectural changes were...
Generation of particle defects in semiconductor manufacturing is inevitable, but it has to be minimized for high IC yield. There are various causes for the generation of particle defects, depending upon semiconductor manufacturing processes. This work discusses various strategies, such as clean on go, idle paste, kit hardware selection that help to reduce the generation of defects in metal thin films...
The ever-shrinking world of semiconductors has always challenged the interplay of tool capability, process integration, and characterization. The fine line between structural or electrical success and failure has steadily been redefined from microns to nanometers with leading edge technology using terms with the likes of angstroms and layers of atoms. Failure modes at these nodes become increasing...
The topic of this manuscript is the development and usage of a Run to Run Controller for etching systems. The system uses dynamic status values and can be operated in different modes. This allows manufacturing high accuracy critical dimensions for contacts or vias.
This article describes a new tool and process for Cu electroplating on power chips. The tool enables a new, more efficient method for embedding power chips by means of simultaneous electroplating on both sides of the wafer. Additional tool features, to be discussed in this article, provide technical benefits for embedded technologies and enable further miniaturization of power chip packages to comply...
Silicon Photonics is a promising new technology for realizing efficient, high performance interconnects. There is a growing need for educating future engineers on how to design, fabricate, test and package Silicon photonic circuits. Here we demonstrate a Silicon photonic process suitable for an educational institution with i-line lithography capabilities. We have developed a suitable process for realizing...
We describe a new delayering solution for semiconductor quality control and failure analyses using low-energy, broad-beam argon ion milling. The results show a large, delayered area, suitable for high resolution scanning electron microscopy (SEM) investigation and energy dispersive X-ray spectroscopy (EDS) characterization. The technique allows full top-down deprocessing, layer by layer, of three-dimensional...
Advanced electronic materials called precursor molecules are designed for the deposition of thin films that are expected to be reliable, contamination free and pristine. Deleterious effects of metallic contamination have been demonstrated in dielectric properties of thermal oxides grown on silicon [1]. In order to achieve ultra-high purity products, essentially free from trace metals (TM) and organic...
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