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Data intensive workloads increase significantly bandwidth and power pressures to the memory system. One possible solution is processing-in-memory (PIM) which moves several logic components into the main memory to accelerate the logic computation. Recently, the concept of processing-in-nonvolatile-memory (PINVM) was proposed to against the technology issue in which the DRAM and logic technology require...
Memories are currently a real bottleneck to design high speed and energy-efficient systems-on-chip. A significant increase of the performance gap between processors and memories is observed. On the other hand, an important proportion of total power is spent on memory systems due to the increasing trend of embedding volatile memory into systems-on-chip. For these reasons, STT-MRAM (Spin-Transfer Torque...
Non-volatile 3D FPGA research to date utilizes layer-by-layer stacking of 2D CMOS / RRAM circuits. On the other hand, vertically-composed 3D FPGA that integrates CMOS and RRAM circuits has eluded us, owing to the difficult requirement of highly customized regional doping and material insertion in 3D to build and route complementary p- and n-type transistors as well as resistive switches. In the layer-by-layer...
The power, reliability and technological issues of today's memories have led to intensive research of emergent memory technologies and emerging computing paradigms. One of the most promising emerging technology solution is the Spin-Transfer-Torque Magnetic Random Access Memories (STT-MRAMs). It has the great advantage of favoring increasing system complexity and performance, while being CMOS compatible...
In this paper, a self-calibrating low power sense amplifier has been proposed to generate true random bits by exploiting random switching behavior of a straintronic MTJ. This circuit has applicability in cryptography in which high quality random numbers are crucial for enhanced security. Digital self-calibration mechanism is employed to accommodate manufacturing variations and slow-temporal changes...
Design for power-delivery network (PDN) is one of the major challenges in 3D IC technology. In the typical layer-by-layer stacked monolithic 3D (M3D) approaches, PDN has limited accessibility to the device layer away from power/ground source due to limited routability and routing resources in the vertical direction. This results in an incomplete and low-density PDN design and also severe IR-drop issue...
This paper presents the designs of two digital circuits in which processing of data (stored in volatile and non-volatile memories) is locally performed and routed; these circuits are referred to as data-centric and therefore, amenable to Near-Memory (NM)operation. Two circuits are proposed; they utilize at logic level a 2-2AOI gate, but with different types of selector. Simulation results using HSPICE...
In this paper, we propose a bias field free Spin Hall Nano Oscillator (SHNO) device with perpendicular-to-plane magnetic anisotropy for alternative computing. Coupled oscillator networks can be used to perform computations such as edge detection of an image, associative computing, etc. that are unsuitable (inefficient) in von-Neumann computing models. Recent experiments on SHNOs have demonstrated...
CMOS scaling faces numerous challenges, among which device scaling, interconnect bottleneck, high leakage power and manufacturability are major ones. The scaling challenge is particularly acute for SRAM since maximum performance/power at highest density is required with every new generation. 3-D integration provides possible pathways to overcome the impediments faced in achieving ultra-high density...
This research proposes a novel approach with vertical design space exploration (DSE) of several levels of configurable architecture design using Beyond Moore devices. ferrimagnets, Multistate Electrostatically Formed Nanowire transistors (MSET), and Magnetoresistive Random Access Memories (MRAM) are first set of devices used to explore the architectural space. Machine Learning (ML) and other scientific...
We present the first Verilog-A based models of a magneto-electric magnetic tunnel junction (ME-MTJ) based XNOR and NOR logic gates. The ME-MTJ is a low-power beyond-CMOS technology, with possible applications in memory and logic devices. The models presented here have been developed in Verilog-A and validated with simulations using cadence spectre. We show the operation of this ME-MTJ dual-purpose...
Memristors have successfully been used to build efficient reservoir computers. The power consumption of memristive reservoirs, however, is bounded by the resistive nature of such devices. Here, we show that memcapacitors, another device in the mem-device family, offer great promise for power-efficient reservoir computers. We simulated memcapacitive reservoirs with two different device models and benchmarked...
With Moore's law approaching physical limitations of transistor size, researchers have started exploring unconventional ways for performing computing. This has led to the discovery of several emerging devices for computing. One such recently discovered device is memristor; it can be used both for storage and in-memory computing. It can also be easily mass produced in the form of compact crossbars...
Three-Independent-Gate Field Effect Transistors (TIGFETs) are capable of different modes of operation thanks to their additional gate terminals. By electrically controlling their side gates, TIGFETs can act either as a p-type or an n-type transistor and can also implement multi-threshold logic. This versatility can be used to create compact logic gates intended for high-performance or low-leakage...
In this paper we propose a novel error correction scheme/architecture specially tailored for polyhedral memories which: (i) allows for the formation of long codewords without interfering with the memory architecture/addressing mode/data granularity and (ii) make use of codecs located on a dedicated tier of the 3D memory stack. For a transparent error correction process we propose an online memory...
In this work, novel magnetic memory device is proposed based on fascinating Spin Momentum Locking (SML) materials. The device utilizes direct spin current to charge current conversion and don't need Magnetic Tunneling Junction (MTJ) structure. The NOR, NAND and 3D array structure of the proposed magnetic memory device are demonstrated and discussed.
Multi-state logic presents a promising avenue for more-than-Moore scaling, since efficient implementation of multi-valued logic (MVL) can significantly reduce switching and interconnection requirements and result in significant benefits compared to binary CMOS. So far, traditional approaches lag behind binary CMOS due to: (a) reliance on logic decomposition approaches [4][5][6] that result in many...
RRAM (memristive) neural networks have shown great potential to implement massively parallel neuromorphic systems. In this work, we propose a hybrid neural network architecture that utilizes reliable binary RRAM devices to perform semianalog computing. The presented system is tested for dictionary learning and analog image compression, where the effect of synaptic weight precision is analyzed.
Modern neuromorphic deep learning techniques, as well as unsupervised techniques like the locally competitive algorithm, rely on Vector Matrix Multiplications (VMMs). When designing biologically-inspired circuits, a VMM is used to represent synapse weighting between neighboring neurons. In hardware, this means that efficient implementations of VMMs are desirable for ASICs implementing neuromorphic...
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