The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
This paper deals with the integration of several emerging technologies (embedded DRAM (eDRAM) and Phase Change Memory (PCM)) with SRAM to leverage their operational features and achieve a hybrid L2 cache for improvements in density and power consumption. A novel hybrid cache replacement and migration policy is proposed; a hybrid macrocell is also designed using a different number of eDRAM, PCM and...
This paper presents the designs of two digital circuits in which processing of data (stored in volatile and non-volatile memories) is locally performed and routed; these circuits are referred to as data-centric and therefore, amenable to Near-Memory (NM)operation. Two circuits are proposed; they utilize at logic level a 2-2AOI gate, but with different types of selector. Simulation results using HSPICE...
In this paper we propose a novel error correction scheme/architecture specially tailored for polyhedral memories which: (i) allows for the formation of long codewords without interfering with the memory architecture/addressing mode/data granularity and (ii) make use of codecs located on a dedicated tier of the 3D memory stack. For a transparent error correction process we propose an online memory...
The influence of realistic experimental constraints of memristor crossbar array on dictionary learning was investigated. A solution with epsilon-greedy strategy was proposed to improve training.
The power, reliability and technological issues of today's memories have led to intensive research of emergent memory technologies and emerging computing paradigms. One of the most promising emerging technology solution is the Spin-Transfer-Torque Magnetic Random Access Memories (STT-MRAMs). It has the great advantage of favoring increasing system complexity and performance, while being CMOS compatible...
The increased capacity of multi-/triple-level cells (mlc/tlc) in phase change memory (pcm) comes at the cost of higher write latency and energy, primarily due to consecutive short programming pulses in the pcm program-and-verify (p&v) approaches. l3ep is a regression-based low latency, low energy tlc pcm p&v solution. l3ep reaches the target tlc state in just one (at most five) pulse(s) for...
Three-Independent-Gate Field Effect Transistors (TIGFETs) are capable of different modes of operation thanks to their additional gate terminals. By electrically controlling their side gates, TIGFETs can act either as a p-type or an n-type transistor and can also implement multi-threshold logic. This versatility can be used to create compact logic gates intended for high-performance or low-leakage...
Memories are currently a real bottleneck to design high speed and energy-efficient systems-on-chip. A significant increase of the performance gap between processors and memories is observed. On the other hand, an important proportion of total power is spent on memory systems due to the increasing trend of embedding volatile memory into systems-on-chip. For these reasons, STT-MRAM (Spin-Transfer Torque...
In this work, novel magnetic memory device is proposed based on fascinating Spin Momentum Locking (SML) materials. The device utilizes direct spin current to charge current conversion and don't need Magnetic Tunneling Junction (MTJ) structure. The NOR, NAND and 3D array structure of the proposed magnetic memory device are demonstrated and discussed.
In this work, a novel Spin Torque Nano Oscillator (STNO) device which can sustain high frequency oscillation without demand of bias magnetic field is proposed. Voltage Controlled Magnetic Anisotropy (VCMA) effect is employed to increase perpendicular anisotropy field leading to high oscillation frequency in the absence of bias magnetic field. In addition, VCMA effect also can be utilized as frequency...
The considerable power consumption on logic and memory circuit system will be an unavoidable bottleneck with the shrinking of complementary metal oxide semiconductor (CMOS) technology size. One promising solution is to build non-volatile spintronic device, e.g. spin transfer torque magnetic random access memory (STT-MRAM). The basic storage unit of STT-MRAM, i.e. magnetic tunnel junction (MTJ), has...
While standalone Flash memories (NAND) are facing their physical limitations, the emergence of resistive switching memories (RRAM) is seen as a solution for high density, low cost and low energy NAND replacement candidate. However, it has been shown that deeply scaled, high density RRAM architectures, such as crosspoint, suffer of voltage drop effects (IR drop) in metal lines, periphery overhead and...
As CMOS technologies reach their physical limits, advanced devices and circuit structures are needed to enable compact circuit design. Carbon nanotube field-effect transistors (CNTFETs) are compelling alternatives to MOSFETs, and their ambipolarity provides a route to reduce device count through higher expressive power with dual-gate CNTFETs. However, previous models do not permit switching of the...
We introduce a new compact in-memory computing design for implementing 8-bit addition using eight vertically-stacked nanoscale crossbars of one-diode one-memristor 1D1M switches. Each crossbar in our design only has 5 rows and 4 columns. Hence, the design may be used to fabricate a compact 8-bit adder that meets the size constraint of 50nm χ 50nm χ 50nm imposed by the electrical component of the Feynman...
Design for power-delivery network (PDN) is one of the major challenges in 3D IC technology. In the typical layer-by-layer stacked monolithic 3D (M3D) approaches, PDN has limited accessibility to the device layer away from power/ground source due to limited routability and routing resources in the vertical direction. This results in an incomplete and low-density PDN design and also severe IR-drop issue...
Non-volatile 3D FPGA research to date utilizes layer-by-layer stacking of 2D CMOS / RRAM circuits. On the other hand, vertically-composed 3D FPGA that integrates CMOS and RRAM circuits has eluded us, owing to the difficult requirement of highly customized regional doping and material insertion in 3D to build and route complementary p- and n-type transistors as well as resistive switches. In the layer-by-layer...
RRAM (memristive) neural networks have shown great potential to implement massively parallel neuromorphic systems. In this work, we propose a hybrid neural network architecture that utilizes reliable binary RRAM devices to perform semianalog computing. The presented system is tested for dictionary learning and analog image compression, where the effect of synaptic weight precision is analyzed.
Analog implementations of neuromorphic circuits within digital systems are increasingly becoming attractive due to the high throughput and low energy per operation they offer. Magnetic logic devices based on spin-orbit torque offer a pathway to low-power resistive analog circuits. We present the magnetic tunnel junction (MTJ) function evaluator, a design for a logic device that evaluates nonlinear...
In this paper, we propose a bias field free Spin Hall Nano Oscillator (SHNO) device with perpendicular-to-plane magnetic anisotropy for alternative computing. Coupled oscillator networks can be used to perform computations such as edge detection of an image, associative computing, etc. that are unsuitable (inefficient) in von-Neumann computing models. Recent experiments on SHNOs have demonstrated...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.