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Stabilization of ferroelectric negative capacitance (NC) in a transistor gate stack is a promising pathway towards future low power electronics. However, most modeling efforts of such NCFETs are based on single-domain Landau theory, which is an oversimplification that leads to incorrect predictions and device design. By extending the Landau model to describe more than one domain, it is shown how an...
In this work, DC and low frequency noise have been investigated in Gate-All-Around Nanowire MOSFETs at very low temperatures. Static characteristics at 4.2 K exhibit step-like effects that can be associated to energy subbands scattering. The mobility and subthreshold swing are also investigated. Finally the low frequency noise spectroscopy (from 10 K to 70 K) leads to the identification of silicon...
We demonstrate for the first time the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) with low temperature (LT) processes devoted to 3D sequential integration. The electrical behavior of these TFETs, with junctions obtained by Solid Phase Epitaxy Regrowth (SPER), is analyzed and compared to reference samples (regular process at high temperature, HT). The threshold voltage...
A simulation study on the impact of interface traps (ITs) and strain on the I/V characteristics of co-optimized n- and p-type tunnel field-effect transistors (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out using a full-quantum simulator. In order to capture the effect of interface/border traps on the device electrostatics in a way consistent with the ballistic approach,...
With the advent of Wireless Sensor Networks and the Internet of Things, the need for energy efficient components has increased significantly. Sensors consume sometimes a significant part of the energy budget of an autonomous system, while it is not always clear how to make them more efficient. Here we attempt to identify strategies for lowering power consumption in transducers. The discussion is constructed...
A novel method for surface charge sensing using the Ψ-MOSFET is presented. Systematic measurements of out-of-equilibrium body potential were performed on SOI wafers. The interest of Ψ-MOSFET as a biochemical sensor is experimentally proved. The advantages of this method are good sensitivity, simplicity and low-voltage reading compared to the conventional ID-VG method.
We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in transistor mode, with back-gate biasing. These devices featured P-type field-effect characteristics suitable for future use as sensors. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as effective low field...
We present a DC-AC Hall-effect analysis on transition-metal-dichalcogenides comprising natural crystals of molybdenum disulfide and tungsten diselenide; and synthetic crystals of hafnium diselenide, molybdenum ditelluride, molybdenum diselenide and niobium-doped molybdenum disulfide. We observe a wide range of Hall mobility and carrier concentration values with either a net electron or hole carrier...
Resistive memories (RRAM) are attracting a wide interest as candidates for the next generation memory technology, in particular for embedded and, more generally, for low power applications like IoT. However, their variability still remains a concern as the latter has been proven to be an intrinsic feature linked to the filamentary switching mechanism. In this paper we will review some recent key results...
Common problems with oxide-based Resistive RAM (ReRAM) are related to high variability in operating conditions and low yield. At array level, ReRAM memory cells suffer from different voltage drops seen across the cells due to the line resistances. Although research has taken steps to resolve these issues, variability combined with resistive paths remain an important characteristic for ReRAM. In this...
In this paper a static noise margin (SNM) analysis is done for an 8T SRAM cell build up with complementary tunnel-FETs (TFETs). The simulations are done with the help of a Verilog-A implemented 2D DC compact model for a double-gate (DG) TFET, published in [1]. The compact model is adapted to measurement data of fabricated nanowire (NW) GAA TFETs before analyzing the hold/read and write SNM of the...
This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM...
We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles with a memory capacitor structure. Our approach is based on the use of indium oxide (In2O3) nanoparticles (or nanocrystals NCs) embedded in a dielectric matrix as a charge trapping layer using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for...
We review the operation mechanisms of the Z2-FET underlining its attractiveness as a capacitorless DRAM memory. The main parameters that govern the memory performance are discussed based on systematic experiments and simulations.
Memory cell selection for 28 nm and beyond and its integration into new eNVM technology have been investigated through atomic layer deposition (ALD) HfO2 resistive memory devices. Both amorphous and crystalline HfO2 layers exhibit promising switching characteristics. It was shown that more than 3 times less power is required to activate the memory device fabricated using the amorphous layer. The forming...
A systematic study to model and characterize the band-modulation Z2-FET device is developed. Emphasis is given on the effect of carrier lifetime which is the key parameter. It provides guidelines to design Z2-FETs for sharp switching, ESD protection and 1T-DRAM applications. We provide new insights of the relation between carrier generation/recombination and electrostatic barriers.
This paper studies for the first time the low temperature characteristics of strained SOI FinFETs submitted to proton irradiation. Both types of transistors, nMOS and pMOS, were analyzed from room temperature down to 100K, focusing on the threshold voltage (VTH), subthreshold swing (SS), the Early voltage VEA and the intrinsic gain voltage (AV). The effects of strain techniques are also studied. The...
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