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Mobile communication and navigation devices have fueled the demand for low power implementations to enhance battery life. A critical aspect of reducing power in these devices is the efficiency of the process of converting power from the battery to the various loads in the system. This makes high-efficiency DC-DC switching power converters a natural candidate for such task. Unfortunately, however,...
This brief presents the SoC-FPGA implementation of the modified Nearly Optimal Sparse Fast Fourier Transform (sFFT) algorithm. The implementation was carried out by using hardware/software co-design based on software profiling that helped to find out that pseudo-random Spectral Permutation, Windowing, and Sub-Sampling (SPWS) are the signal processing operations that require most processing time in...
In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
High density embedded memories have been demanded increasingly to enhance the performance and reduce the power dissipation of advanced systems, such as multicore processors, which have been used in a wide variety of applications from servers to Internet-of-things (IoT) devices. In this paper, a memory cell, referred to as the gain-cell magnetoresistive random access memory (gMRAM), is introduced....
For a growing pool of data-intensive applications, data transfer, rather than processing speed, has emerged as the major bottleneck to performance and energy scalability. In this paper, we propose a novel interleaved logic-in-memory architecture, referred to as MISK, which leverages fine-grained integration of logic functions within dense, 2-D static random-access memory (SRAM) arrays for in-situ...
Ferroelectric RAM (FRAM) is a non-volatile memory with fast, low power, high endurance, read and write operations. Hence, this technology remains an attractive choice for embedded system solutions. In this paper, we analyze Si data that initiated the effort to design a compensated Sense Amplifier (SA) with improved input offset-sigma. We evaluate the cost vs benefit tradeoffs associated with this...
Random number generators (RNGs) are an integral component of numerous stochastic simulation methods, with applications in diverse scientific disciplines. Recently, stochastic simulation methods are being increasingly implemented on FPGAs for improved performance. Consequently, efficient RNG implementations are essential to successfully realize stochastic simulation methods on FPGAs. We present a memory...
The advancing trend to autonomous driving tightens the requirements for automotive microcontrollers with embedded flash memories. High reliability and low latency demands however have prevented the broad usage of multilevel-cell flash in this sector so far. This paper describes a robust time-domain voltage sensing scheme tackling the challenges arising from these tight conditions. A dynamic voltage...
The spin transfer torque magnetic random access (STT-MRAM) is suitable for embedded memories and also for the second level cache memory in the mobile CPU's. The most capable NVM component is STT-MRAM, which enhances the performance by 3.3 nS access time. It has strong radiation hardness, higher integrity and maximum endurance compared to SRAM. The power consumption of STT-MRAM is decreased by an order...
The spin transfer torque magnetic random access (STT-MRAM) is suitable for embedded memories and also for the second level cache memory in the mobile CPU's. The most capable Nonvolatile memory (NVM) component is STT-MRAM. There is a demand to improve efficient circuit and architecture to compete with the existing NVM technologies. Low energy consumption is achieved to write and read into MTJ. This...
In a world where electronics is becoming increasingly ubiquitous, the challenge of powering devices is progressively becoming more difficult. Often it is impractical to replace batteries or line power numerous devices. Energy harvesting is an attractive alternative but has the inherent disadvantage of frequent power loss. For processing systems like microcontrollers (MCUs) power restoration usually...
Computer architecture today is anything but business as usual, and what is bad for business is often great for science. As Moore's Law continues to unwaveringly march forward, despite the ceasing of Dennard scaling, continued performance gains with each processor generation has become a significant challenge, and requires creative solutions. Namely, the way to continue to scale performance in light...
Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses short-channel effects by providing superior electrostatic control over the channel. Due to the unique device structure, gate-all-around nanowire transistor also allows more efficient layout design by exploiting 3-dimensional stacking...
A 4 kb fully differential 8-port SRAM bitcell array (6 read ports and 2 write ports) is presented in this paper. This 8-port SRAM provides simultaneous access, high system throughput and a great read static noise margin by isolating the read ports from storage nodes. At 0.4 V supply voltage, designed 8-port SRAM bitcell shows 123, 137 and 123 mV static noise margin during read, write and standby modes,...
True Random Number Generators (TRNG) are used in a variety of applications including cryptographic algorithms, communication systems, simulations, etc. From a security perspective, TRNGs are particularly important because they can produce random output bits that are fully unpredictable and unbiased. Random sources are not often apparent and it is useful to have intrinsic hardware-based random number...
The Static Random Access Memory (SRAM) directly impacts the performance of the modern multi-core processor. Hence, the power, performance and area metrics are very crucial for SRAM design. In this article, we have successfully designed 10 nm TFET based 6T SRAM circuit at reduced supply voltage of 0.5 V. We also have optimized the circuit for high density, high performance, intermediate (trade-off...
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