The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a CMOS image sensor with high conversion-gain pixels and column-shared pipelined ADCs for Fluorescence-lifetime imaging microscopy (FLIM). Pixel conversion gain of 121 uV/e-is achieved by creating a distal floating diffusion from transfer gate and reset transistor gate without any process modification. 32-channel 10-bit on-chip column-shared pipelined ADCs with sampling rate up...
This paper introduces a multi-loop fast transient response flipped voltage follower (FVF) low-dropout (LDO) voltage regulator suitable for system-on-chip (SOC) applications. While typical FVF-based LDOs exhibit fast transient response, which is critical for SOC applications, their output DC accuracy is limited due to low loop gain of the FVF. In this work, we introduce a multi-loop design aimed at...
The flipped voltage follower (FVF), a variant of the common-drain transistor amplifier, comprising local feedback, finds application in circuits such as voltage buffers, current mirrors, class AB amplifiers, frequency compensation circuits and low dropout voltage regulators (LDOs). One of the most important characteristics of the FVF, is its low output impedance. In this tutorial-flavored paper, we...
A Look-Up Table (LUT) shows modest performance (delay and power) when used as a universal logic module (ULM) for implementing all possible combinational functions; moreover, the complete programmability of a LUT (so for all functions) incurs in a significant circuit complexity. Few approaches have been proposed by which a LUT is replaced by circuits; this is possible because in practice, the number...
In this paper, we present a multi-string LED driver which is capable of driving five parallel LED strings with two series LEDs in each string. The current in the LED strings is regulated using a boost converter with a hysteretic control loop. Accurate current matching is achieved using a regulated cascode current mirror architecture. The loser-take-all circuit enables dynamic cancellation of LED forward...
In this paper, an low power CMOS temperature sensor for implantable applications is implemented in a 0.18 μm CMOS process. Sensors for implantable devices must have sub-μW power consumption to avoid tissue overheating. Thus, this temperature sensor employs subthreshold MOS transistors as the sensing element to reduce power consumption and enable minimum supply voltage. Temperature is converted to...
This paper presents an open-loop 28GHz 16-phase clock generator in 28nm CMOS technology. The open loop architecture is composed of 22.5° delay units and uses phase compensation to account for delay time variations. The 16-phase 28GHz clock generator consumes 14mW, leading to a power efficiency of 0.032mW/GHz/phase. The maximum phase error is 6° and the RMS phase error is 3° when the input frequency...
High-level synthesis is increasingly being used to automatically translate existing software algorithms into hardware quickly and efficiently. Typically, the circuits created by HLS are implemented on Field-Programmable Gate Arrays (FPGAs). While the fine-grained architecture of an FPGA is well suited for general circuit implementation, it can result in excessive routing resource utilization for larger...
High density embedded memories have been demanded increasingly to enhance the performance and reduce the power dissipation of advanced systems, such as multicore processors, which have been used in a wide variety of applications from servers to Internet-of-things (IoT) devices. In this paper, a memory cell, referred to as the gain-cell magnetoresistive random access memory (gMRAM), is introduced....
Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU...
A Li-ion battery charger with dual input source capability and high efficiency is proposed in this work. An internal source determination circuit could choose the sufficient energy source for charging system. Also, a new approach of smooth transition to avoid oscillation between charging mode switching is used through current-mode-like smooth transition circuit. Pulse frequency modulation with adaptive...
Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario,...
A novel offset calibration technique with fast convergence rate for high-speed dynamic comparators is presented. The circuit utilizes a multi-rate charge pump circuitry to speed up the calibration process while maintaining the precision which leads to better energy efficiency. The circuit is designed in a 0.13μm CMOS process. Based on Monte-Carlo simulation results the comparator achieves 183.1μV...
With the increase in usage of low-power electronics in security critical area, demand for secure transmission of private and confidential information is on the rise. Implementation of dedicated hardware for cryptography is essential nowadays, even in the resource-constrained devices, to meet high-security concerns. However, hardware implementation of cryptographic algorithms may result in security...
The spin transfer torque magnetic random access (STT-MRAM) is suitable for embedded memories and also for the second level cache memory in the mobile CPU's. The most capable NVM component is STT-MRAM, which enhances the performance by 3.3 nS access time. It has strong radiation hardness, higher integrity and maximum endurance compared to SRAM. The power consumption of STT-MRAM is decreased by an order...
A hybrid voltage-mode hysteretic boost converter is introduced in this work. The implemented control topology is practically self-stabilized due to the introduction of a current-limiting loop. A full range inductor current sensor and a hysteretic comparator are used to realize the current-limiting loop. A zero current detector is also implemented to enable a seamless transition from continuous to...
The spin transfer torque magnetic random access (STT-MRAM) is suitable for embedded memories and also for the second level cache memory in the mobile CPU's. The most capable Nonvolatile memory (NVM) component is STT-MRAM. There is a demand to improve efficient circuit and architecture to compete with the existing NVM technologies. Low energy consumption is achieved to write and read into MTJ. This...
A CMOS Crystal Oscillator with automatic amplitude control (AAC) is presented which occupies low area and consumes lower current when compared to existing state of the art designs. Amplitude control loop based implementations of low frequency crystal oscillators usually achieve low-power operation at the expense of die area. The proposed design aims at reducing the overall area by replacing the bulky...
In this paper, the sensitivity of the optical receiver is revisited. An analytical expression that reveals the dependency of the sensitivity on both the data rate (fbit) and the bandwidth shrinkage factor (n) is derived. The proposed sensitivity model provides guidelines for selecting the front-end topology. Based on that model, a three-stage front-end is implemented in 65 nm CMOS technology and 18...
This paper proposes a novel fully differential ultra-low voltage transimpedance amplifier (TIA) based on a CMOS translinear circuit. Following a simple bias strategy, its transimpedance gain can be adjusted to the desired accuracy either by means of an external resistor or using internal voltage and current references. To a first order approach, the transresistance results independent from technological...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.