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Fault injection testing approaches assess the reliability of execution environments for critical software. They support the early testing of safety concepts that mitigate the impact of hardware failures on software behavior. The growing use of platform software for embedded systems raises the need to verify safety concepts that execute on top of operating systems and middleware platforms. Current...
Hardware simulators are indispensable tools for the computer architecture research. They are used by the academia and industry to prototype, explore and evaluate novel microarchitectural features.
Exascale computing will get mankind closer to solving important social, scientific and engineering problems. Due to high prototyping costs, High Performance Computing (HPC) system architects make use of simulation models for design space exploration and hardware-software co-design. However, as HPC systems reach exascale proportions, the cost of simulation increases, since simulators themselves are...
Information Flow Tracking (IFT) provides a formal methodology for modeling and reasoning about security properties related to integrity, confidentiality, and logical side channel. Recently, IFT has been employed for secure hardware design and verification. However, existing hardware IFT techniques either require designers to rewrite their hardware specifications in a new language or do not scale to...
In the past decade, the number of reported security attacks exploiting unchecked input firmware values has been on the rise. To address this concerning trend, this work proposes a novel detection framework, called DOVE, capable of identifying unlikely firmware execution flows, specifically those that may reveal a security vulnerability. The DOVE framework operates by leveraging a symbolic simulation...
Computer systems software and hardware architectures have become increasingly complex today. Meanwhile, cyberattacks are becoming more and more sophisticated and target any software or hardware components of these systems. Several isolation mechanisms, at the software and the hardware layers, are now available to provide the best protection against these widespread attacks. This paper is aimed at...
We propose an approach for overapproximating the Worst-Case Execution Time (WCET) of embedded control software using formal methods. Model checking is iteratively applied to compute the WCET from the machine code of the software considering a platform and an environment model. We implemented the approach and present first experiments for a thermal controller application executed on a LEON3 processor...
Software defines the functionality of today's Cyber-Physical Systems (CPS). Many product innovations are based on software and thus the complexity of software, even when running on platforms equipped with small microprocessors, is increasing dramatically. This calls for adequate embedded software integration testing, even before the actual hardware platform is available. The application of virtual...
Split-execution computing leverages the capabilities of multiple computational models to solve problems, but splitting program execution across different computational models incurs costs associated with the translation between domains. We analyze the performance of a split-execution computing system developed from conventional and quantum processing units (QPUs) by using behavioral models that track...
This paper describes a methodology for system-level security verification of modern Systems-on-Chip (SoC) designs. These designs comprise interacting firmware and hardware modules which makes verification particularly challenging. These challenges relate to (i) specifying security verification properties, and (ii) verifying these properties across firmware and hardware. We address the latter through...
Computer designers rely upon near-cycle-accurate microarchitectural simulators to explore the design space of new systems. Hybrid simulators which offload simulation work onto FPGAs (also known as FAME simulators) can overcome the speed limitations of software-only simulators. However such simulators must be automatically synthesized or the time to design them becomes prohibitive. Previous work has...
This work introduces a methodology for the modelization of network functions focused on the identification of recurring execution patterns and aimed at providing a platform independent representation. By mapping the model on specific hardware, the performance of the network function can be estimated in terms of maximum throughput that the network function can achieve on the specific execution platform...
The ARM simulator not only eliminates the barriers of embedded systems' hardware environment, but also improves the efficiency, security and reliability for the development process. To improve the performance of an ARM-based function simulation, a novel simulation framework to the ARM processor is proposed, which is based on the ARM instructions' eigenvalue. Therein, functions of registers, the instruction...
Future generation processors are expected to have high soft error rates and will require increased fault detection and fault tolerance. This work focuses on errors in execution units. Hardware or software duplication or triplication, parity, or residue codes could be used to detect errors in execution units. However, hardware duplication/triplication have significant area overhead and, in applications...
In many cases, applications are not optimized for the hardware on which they run. Several reasons contribute to this unsatisfying situation, including legacy code, commercial code distributed in binary form, or deployment on compute farms. In fact, backward compatibility of ISA guarantees only the functionality, not the best exploitation of the hardware. In this work, we focus on maximizing the CPU...
Heterogeneous dynamic computing platforms are one of the big trends in today's electronic world. These platforms typically feature different General-Purpose-Processors (GPP) combined with accelerators on a reconfigurable layer. However, this necessitates specialized programming models and an Operating System (OS) for dealing with the dynamicity. To allow the early development of the system software,...
The interacting visual maps (IVM) algorithm introduced in [1] is able to perform the joint approximate inference of several visual quantities such as optic-flow, gray-level intensities and ego-motion, using a sparse input coming from a neuromorphic dynamic vision sensor (DVS). We show that features of the model such as the intrinsic parallelism and distributed nature of its computation make it a natural...
Resiliency of exascale systems has quickly become an important concern for the scientific community. Despite its importance, still much remains to be determined regarding how faults disseminate or at what rate do they impact HPC applications. The understanding of where and how fast faults propagate could lead to more efficient implementation of application-driven error detection and recovery. In this...
In this paper, we propose a Sliding Window Method (SWM) to calculate absolute value based on the stochastic computing. We prove that the absolute value of the stochastic stream can be obtained from the limiting distribution of the Markov chain by establishing a Markov model of SWM. The proposed schemes can be employed to both unipolar and bipolar stochastic streams. The simulation and design reports...
In this paper, we present SADA, a static analysis tool to verify device drivers for TinyOS applications. Its broad goal is to certify that the execution paths of the application complies with a given hardware specification. SADA can handle a broad spectrum of hardware specifications, ranging from simple assertions about the values of configuration registers, to complex behaviors of possibly several...
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