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This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with...
In this paper a side-channel-attack resistant AES system with a variation-tolerant true Random Number Generator (tRNG) is implemented using IBM 0.13μm CMOS technology. As the random source for the AES, a meta-stability based tRNG takes advantage of an all-digital self-calibration method to compensate Process-Voltage-Temperature (PVT) variations, and thus guarantees output with extremely high randomness...
The ability to identify (detect) and categorise (sort) neural spikes in real-time and under highly restrictive power/area budgets is a major enabling technology towards the development of intelligent implantable systems. In this work we propose a memristor-CMOS hybrid architecture concept that relies on a ‘template pixel’ (texel) circuit combining CMOS and memristive devices to perform on-line spike...
This paper presents the design and simulation of an auto-tuning capacitive power transfer (CPT) system based on Class-E converter approach. The reason of selecting Class-E converter is due to the remarkably high efficiency that it can achieve. However, the load's variation affects the output voltage of Class-E converter significantly and increases the switching loss of the system. To regulate the...
A compact CMOS voltage-controlled relaxation oscillator circuit is presented in this paper. The frequency control is fulfilled by using a single MOSFET to control the charging and discharging currents of a timing capacitor. This paper investigates and demonstrates the proposed control mechanism. The proposed VCO was fabricated using 0.18 μm CMOS technology and the fabricated VCO has a compact core...
In this paper, a digitally-controlled oscillator (DCO) with differential output and eight different phases is proposed. The DCO is based on two-path ring oscillator (RO) with cross-coupled structure. The proposed DCO structure consists of four differential stages and two 9-bit digitally-controlled current sources, which guarantee high resolution and monotonic behavior of the DCO. The circuit is simulated...
This paper proposes a new programmable delay cell (PDC) controlled by a 4-bit binary coding inverter array and a 4-bit binary coding capacitor array for the digital impulse radio (IR) ultra wide band (UWB) pulse generator. This proposed PDC can realize an extended tuning range of pulse width with an adjustable step and reduce the cost of chip area. Simulation results show that, when implemented in...
This paper describes experimental results on an orthogonal-core type linear motor with a new control system. This orthogonal-type linear motor has two power supply windings, and the velocity or direction of the moving parts can be easily controlled by regulating the voltage phase difference between the primary power supply winding and the secondary power supply winding. The excellent features of the...
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