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A modified structure of operational transconductance amplifier (OTA) in CMOS 65-nm technology with signal-current enhancer and slew-rate (SR) helper is presented in this paper. The bias current is chosen to be lower than 0.1 μA to reduce the overdrive voltage requirement and thus make the amplifier survive under 0.7 V supply. An SR helper is also introduced to improve the transient performance. As...
A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation mode using ring amplifier and SAR quantizer. Proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order modulator in 90nm CMOS technology. Simulated SNDR of...
This paper presents a biopotential acquisition unit with an instrumentation amplifier and analog-to-information converter for wearable health monitoring applications. The instrumentation amplifier defines the quality of the acquired biopotential signals. At the heart of the system is an Analog to Information Converter (AIC) to enables the random under-sampling operation. AIC is used to digitize the...
In this paper a design of two-stage CMOS operational amplifier for sigma-delta ADC is presented, which operates at ±1.8 V power supply using 180 nm technology. This two-stage CMOS OP-AMP has been designed to indicate a unity gain frequency of 18.2MHz and indicates a gain of 71.27 dB. The design and simulation part has been done on Cadence Custom IC CAD. The simulated results are encouraging and has...
This paper presents a discrete time fully differential CMOS signal conditioning circuit for acquisition of biosignals. It is realized using switched capacitors (SC), which provides reconfigurability, high precision, high CMRR and low sensitivity to temperature and process variations. However, the SC circuit suffers from various errors like charge injection and clock feedthrough which have an impact...
This paper presents a generic model that links the compensation techniques used in two-stage amplifiers to the structures of three-stage amplifiers. Many previous designs can be derived from this model, and new three-stage amplifiers can potentially be constructed. A novel three-stage amplifier based on this generic model is proposed. Simulation results show that the proposed design outperforms many...
A low-power biomedical signal acquisition SoC is proposed for continuous health monitoring system. The SoC fully integrates a low-noise analog front-end (AFE), a current-steering low-pass filter (CSLPF), and an output buffer. A DC-rejection loop and a chopping function are added to enhance the noise performance. For processing various bio-signals, the bandwidth can be adjusted to extract the signals...
A charge pump with power-on reset (POR) circuit is presented. The proposed circuit generates reset signal during supply voltage rising. It uses common capacitor, voltage follower, and current source to make POR signal and later on as usual charge pump. So, it saves the chip area and ensures initial charging of capacitor. Furthermore, the proposed circuit guarantees that reset signal appears when supply...
This paper presents the design and simulation results of a multi-band CMOS low-noise amplifier (LNA) from 1.9GHz to 2.4GHz. Input and output impedance matching networks are achieved with extra variable capacitor controlled by the voltage. The variable capacitors used in the circuit design can make the LNA operate at some key frequency bands between 1.9GHz and 2.4GHz. The LNA is designed using IBM...
This paper presents a very high-speed low-power 10bit pipelined ADC in a 90nm CMOS technology. A modified opamp-sharing technique is proposed which enables merging the S/H and first stage with optimum power saving. The new technique saves power by changing the bias currents of the input and output stages of the amplifier. Stage scaling and low power dynamic comparators are also utilized to reduce...
A 14bit MDAC with 120MS/s conversion rate, in 0.35um CMOS technology is presented. The MDAC consumes a power of 36mW from a 3.3v power supply and its settling time is 7ns. It utilizes a new high speed, high gain Op Amp, with 102dB gain, and 1.2GHz bandwidth. The phase margin of Op Amp is 51° and its settling time is 5ns for feedback gain of 8. The Op Amp has a good linearity of -60dB.
A voltage feedback charge compensation technique is presented to prevent the conversion nonlinearity due to the parasitic effect of split capacitive DAC structure in successive approximation register (SAR) ADCs. The charge compensation is achieved by using an open loop amplifier that performs voltage feedback to the DAC array via a compensation capacitor, which is easy to be implemented with very...
Radio frequency (RF) circuit is having a rapid growth in wireless telecommunication. The increasing demand for higher quality and popularity of wireless services have urged the development of low cost multi-functional and reconfigurable RF front end modules fabricated from advanced device technologies. The RF front end is generally defined as everything between antenna and the intermediate frequency...
A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced in this work. By utilizing active capacitors to realize the compensation network in a nested way, two inverting gain stages can be used as the second and third gain-stages. The proposed scheme reaches better bandwidth-to-power and slew-rate-to-power performances comparing to the ever published...
This paper presents a theoretical study on clock control strategy of four-phase Dickson charge pump for improving the power efficiency. Optimized clock control signals attains better power efficiency when compare the conventional designs. Simulation results based on the 0.25 mum CMOS technology are presented to validate the analysis.
Radiation-hardened-by-design comparators to mitigate Single-Event-Transients (SETs) are presented. Folded cascode comparators are designed using three types of auto-zeroing techniques: input offset storage (IOS), output offset storage (OOS), and auxiliary offset storage (AOS). The designs are implemented using CMOS 90 nm, and analyzed using Spectre from Cadence. Simulation results show that the transient...
This paper presents the design of a reconfigurable successive approximation analog to digital converter (ADC) for both ultra wideband and Bluetooth applications. The behavioral level design is presented along with the circuit implementation. The ADC architecture employs a split capacitor array DAC which reduces the power consumption. The ADC is implemented in a 0.18mum CMOS process and circuit level...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
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