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This paper presents an enhanced voltage reference for Switched-Capacitor ADCs. Charge losing effect is analyzed and quantized. Charge-Compensation-Based (CCB) technique is introduced to reduce the signal-dependent effect. Charge Compensation Unit (CCU) is designed to compensate charge. It features in low overhead on power and chip-size. A proof-of-principle CCB reference design for a 12-bit 500MS/s...
In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by applying the correlated level shifting (CLS) technique for the first four stages. Moreover, by obviating the need for a first stage S/H, power consumption was reduced considerably. The first stage of the pipeline has a 2.5-bit resolution,...
This paper presents a very high-speed low-power 10bit pipelined ADC in a 90nm CMOS technology. A modified opamp-sharing technique is proposed which enables merging the S/H and first stage with optimum power saving. The new technique saves power by changing the bias currents of the input and output stages of the amplifier. Stage scaling and low power dynamic comparators are also utilized to reduce...
This paper presents a novel digital calibration technique for pipelined ADCs, which compensates both sub-DAC and interstage gain error. The proposed calibration technique is very efficient comparing to other existing calibration techniques, in which only additions and subtractions are employed in this algorithm, no multiplication and division is included. The simplicity of the calibration makes it...
This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more...
A low power 12 bits analog to digital converter is a critical part of a fully integrated readout system for the next ILC ECAL. We present here a new design of 12-bit ADC up to 35-MS/s using a pipelined architecture in a CMOS 0.35 m process. The first front-end stage of 2.5 bits includes an efficient dynamic element matching scheme permitting to average its gain errors. The back-end converter is a...
This paper describes a digital calibration scheme for pipelined analog-to-digital converters (ADCs). The proposed method corrects the nonlinearity caused by finite gain and bandwidth of interstage operational amplifiers as well as the capacitors mismatch in multiplying digital-to-analog converters. The proposed calibration technique takes the advantages of both foreground and background calibration...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
In this paper, a 12-bit 50MHz Pipelined Low-Voltage ADC is presented, which consists of 8-stage-pipelined low resolution ADCs and a 4-bit flash ADC. Several critical technologies are used to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, gain-boosted telescopic OTA and so on. Finally the whole system is taped out in SMIC...
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