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Architectural vulnerabilities in basic analog circuits that can be exploited to embed analog hardware Trojans are identified. Challenges of detecting the presence of analog hardware Trojans are discussed. An example is presented of a simple widely used reference generator that incorporates an embedded analog hardware Trojan that requires no extra circuit components, no area overhead, and that leaves...
Polar codes have emerged as the most favorable channel codes for their unique capacity-achieving property. To date, numerous approaches for efficient decoding of polar codes have been reported. However, these prior efforts focused on design of polar decoders via deterministic computation, while the behavior of stochastic polar decoder, which can have potential advantages such as low complexity and...
The complexity of heterogeneous systems has been increased during last years. One challenge of designing these systems is to deal with the application of methodologies based on Model Driven Architecture (MDA). MDA is a development framework that enables the description of systems by means of different models with transformations. This is an important area of research and consists on developping methodologies...
Dual Tone Multi Frequency signal detection is an important to developing for telecommunication equipment. "This is a standard where keystrokes from the telephone keypad are translated into dual tone signals over the audio link". FPGA has gains very popularity in recent years due to their reprogram ability and flexibility. This paper presents a new type of ZYBO Board ZYNQ 7000 series FPGA...
With the increase in wireless communication technology, encryption of information sent has become a major concern. This involves both the software level and hardware level encryption. GSM was the first cellular system that paid attention to secure mobile communication. Before the advent of GSM the cellular system had no particular security. The GSM voice calls are encrypted using a family of algorithms...
Many types of stochastic algorithms, such as Monte-Carlosimulations and Bit-Error-Rate testing, require veryhigh run-times and are often trivially parallelisable, so are natural candidates for execution using FPGAs. However, the applications are reliant on Gaussian Random Number Generators (GRNGs) with good statistical properties, as very small biases over trillions of random samples can lead to incorrect...
As part of a larger project to build a laboratory-based smart grid feeder, there was a need to incorporate renewable energy sources into the feeder model. The goal in this project was to create a hardware-in-the-loop (HIL) wind turbine simulation platform. Software is used to calculate a dynamic optimal power point from time-series wind speed data and to generate control signals for the platform’s...
We propose in this paper a new hardware architecture for implementing the hyperchaotic Lorenz generator using FPGA technology. The goal is to design a new complex chaotic system which can be used as an unidentifiable key generator in embedded cryptosystems. The proposed architecture provides good performances in terms of throughput and resources cost required for highly secure communications between...
A novel FCSR-based generalized self-shrinking stream sequence generator (called F-GSS) has been proposed. The F-GSS keystream generator has passed the NIST's statistical test suite, which shows that F-GSS has good pseudo-random properties, and the ESTREAM's test suite, which shows the efficiency of F-GSS, in terms of high encryption rate for long streams, high encryption rate for different packets,...
In this paper, procedural texture mapping based on Perlin noise is firstly implemented and simulated in Matlab. And then the design is converted from float-point to fix-point in Simulink. Using the system modeling tool, System Generator from Xilinx company, the noise function can be directly mapped into FPGA hardware. From the experimental results, various graphical textures can be implemented in...
The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI design and test-error-tolerance (ET), we managed to develop a novel error-tolerant adder which we named the Type II (ETAII). The circuit to some extent is able to ease...
This article proposes a method which reduces delay and area in EDAC circuits. A SEC-DED Hsiao code (39,32) and a DEC systematic (1 6, 8) code used for the hardware implementation of EDAC, are discussed and compared. Two codes are all proposed by the authors in earlier paper. In terms of parity-check matrix of these codes, this article presents a low-cost generation method of check bits. Simulation...
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