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Adders are one of most essential components of the digital circuits that are designed for different DSP applications. The important aspects considered for designing any digital circuit design are delay, power and Power Delay Product (PDP). In this paper, 32 bit carry bypass adders (CBA) which have superior performance with respect to these parameters are presented. The CBA's are implemented using...
Approximate or inexact computing has recently attracted considerable attention due to its potential advantages with respect to high performance and low power consumption. This paper presents the design of an approximate multiplier; this approximate multiplier consists of an approximate Booth encoder, an approximate 4-2 compressor and an approximate tree structure. The approximate design is implemented...
With the increasing complexity of electronic circuits and to meet the demand of high performance, the design and optimization of electronic circuits need to be automated with high degree of reliability and accuracy. In order to optimize hardware requirements of digital combinational circuits, evolutionary and innovative techniques need to be enforced at various levels such as at gate level and device...
As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder on a VLSI based embedded application matters. In this paper we primarily deal with the construction of high speed adder circuits. Design...
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed...
XOR-XNOR circuits are the basic building block of many arithmetic and encryption circuits. This paper proposes a low-power 5 transistor XOR-XNOR circuit. This paper also evaluates and compares the performance of various XOR-XNOR circuits. The performance of these circuits are based on 90nm process model at all range of supply voltage starting from 0.6V to 1.2V is evaluated by the comparison of the...
In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good...
The optimization of fixed coefficient FIR filter implementation has been focused mainly on the multiplier block where full precision fixed point arithmetic is normally used. Recently, an optimization method was proposed for the structural adders in FIR filters. This paper further proposes a method for gradually reducing the number of fractional bits within the structural adder block such that the...
The research on optimization of Multiple Constant Multiplication (MCM) during the last two decades has been focusing mainly on common subexpression elimination and reduced adder graph algorithms when bit-parallel computation is required. The advancement of FPGA technology enables the implementation of complex MCM instances on FPGA, but the shift-and-add network implementation does not make full use...
Parallel-prefix adders (also known as carry-tree adders) are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares...
In the majority of the digital designs, adder is the basic building block of the most computational systems. Recently, increasing the speed of adders has been a challenging issue for most of researchers. In this article, a developed adding method is proposed for half adder (HA) based pipeline adders where the output evaluating and latching operations are combined together. As the output functions...
The tradeoff between power consumption and speed performance has become a major design consideration when devices approach the sub-100 nm regime. It is especially critical when dealing with large data set, whereby the system is degraded in terms of power and speed. If the application can accept some errors, i.e. the application is Error - tolerant (ET), a large reduction in power and an increased...
In this paper, two novel structures at 200mV 0.18um sub-threshold full adders are proposed for wireless sensor network nodes or medical electronics. They use three state gate to enhance the transition time and drivability of carry out signal. Simulation results show that the transition time of the proposed structure using three state gate is 60% of that of old structure using transmission gate. The...
In this paper the most interesting topologies of one-bit hybrid full adders, are analyzed and compared for speed, power consumption, and power-delay product. The investigation has been carried out with properly defined simulation set up and input pattern on a Mentor Graphics environment using a TSMC 180 nm CMOS process. Performance has been also compared for different supply voltage values. The simulation...
Full adder is an essential component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors etc. Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance...
This paper presents a new technique for realizing very high-speed CMOS 4-2 compressor which is an essential part in fast digital arithmetic integrated circuits. We have used current mode fully differential circuit technique for designing the compressor circuit. The proposed compressor has been compared to a conventional and a high speed dual-pass transistor logic (DPL) structures. For a fair comparison...
Superconductive rapid single flux quantum (RSFQ) digital computing system has the tendency to achieve the operating rate of several hundred GHz. Compare to the semiconductor partner, with the pulse width about picoseconds and clock rate of several hundred GHz, the timing uncertainty from fabrication process variations makes it impossible to achieve the large scale integrated chip with global synchronization...
This paper presents a high speed low power 4:2 compressor cell design based on Domino Logic circuits. Two circuit level optimizations of 4:2 compressors are proposed by using Split Domino Logic and Multiple-output Domino Logic. All three designed circuits are simulated using HSPICE and compared with each other in terms of delay, power consumption, power-delay product, and operation frequency. Simulation...
The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI design and test-error-tolerance (ET), we managed to develop a novel error-tolerant adder which we named the Type II (ETAII). The circuit to some extent is able to ease...
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