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The downscaling in VLSI systems and the use of new materials influences the reliability of components in terms of radiation more and more. The unavoidable presence of particle radiation on ground and in space leads to unwanted failures in the electronic devices. Concerning packaging materials, design and technology a lot of steps were done to avoid radiation sensitivity. Nowadays microelectronic for...
We investigate the impact of single-event upsets in dynamic flip-flop circuits, which are more appealing for the design of high-performance microprocessors because of short latency, small area and high clock frequency. Previous work either uses the approaches for static flip-flops to evaluate SEU effects in dynamic flip-flops or overlook the SEU injected during the precharge phase. We re-examine the...
Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale...
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET models to accurately capture the nonlinear properties of submicron MOS transistors. Based on these models, we propose and validate the transient pulse generation model and propagation model for soft error rate analysis. The...
The lifetime of integrated chip tends to decrease more and more with technology scaling. To check if a design is robust, in this paper we present RTME (real time MTTF evaluation), a simulation framework that enables the evaluation of reliability at higher level of abstraction layer. Using the output of RTME, we are able to distinguish the effect of different benchmarks on different blocks of the processor.
A CMOS-compatible high voltage multiplexer (HV MUX) for zero-additional-mask CMOS one time programmable (OTP) memory array mask is presented. The HV MUX uses standard CMOS with low input voltage and produce high output voltage beyond the VDD allowed by the process for programming the OTP memory array. By limiting the instantaneous voltage between any two nodes, the HV MUX can tolerate the high voltages...
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
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