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This paper presents the design for a prototype tactical dynamic spectrum access (DSA) mobile ad hoc network, where the network is organized into clusters operating on a single frequency. The frequency may be changed autonomously by the network in response to jamming or interference, after some frequency switching delay. The network node design is implementable on a software defined radio (SDR), such...
Hierarchical routing resources play vital role in FPGA routing. Better routability options can be obtained using segmented approach of wires thus enabling routing optimization. Source and sink logic blocks can be connected via wire segments such that the overall wire length and switching transistors inside the switch box can be saved over an extent. This paper presents an experimental approach of...
In this paper, a novel way to finely tune a net delay on Xilinx Field Programmable Gate arrays (FPGAs) is proposed. It consists of adding floating interconnects (nodes) to the net on which the delay is to be tuned, connected to any input pin of a switch matrix along the net. Adding nodes is made with a TCL script applied to an already placed and routed design. However, such nodes, also called antennas,...
Three-dimensional Field Programmable Gate Arrays (3D FPGAs) represent a viable alternative to overcome challenges of integration complexity in modern embedded systems. Mapping applications into 3D FPGAs requires a set of accompanying suite of Computer-Aided Design (CAD) tools. One of critical issue of a 3D FPGA-based implementation is the quality and efficiency of associated CAD algorithms. In this...
This paper proposes to use the high density of vias enabled by monolithic 3D integration to produce multi-stack FPGA designs with improved performance and functionality. The use of fine grain vertical interconnects enables reconfiguration of FPGA logic within a few clock cycles, as shown in our design that features dynamic reconfiguration capabilities through the use of a pair of configuration memories...
Resistive Random Access Memory (RRAM)-based routing multiplexers, built using a one-level structure, are significantly more delay efficient than state-of-art SRAM-based implementations thanks to their lower achievable on-state resistance. In addition, the delay of RRAM-based multiplexers scales better with respect to input size than SRAM-based multiplexers. This property allows RRAM-based FPGA architectures...
Physical Unclonable Function (PUF) has now become a core lightweight hardware-intrinsic cryptographic primitive for device identification and authentication to secure edge computing in Internet of Things (IoT). The main challenge in most delay-based PUF implementations is the rival of response uniqueness and reliability. Due to routing constraint, implementation of delay-based strong PUF on FPGA tends...
The rapid development of the Internet-of-Things requires hardware that is both low-energy and flexible, and a near/sub-threshold FPGA is a very promising solution. In the design of near/sub-threshold FPGAs, the biggest challenge is reducing global interconnect energy, which is the most energy-consuming part in the entire FPGA. Dynamic voltage scaling is an effective technique in reducing energy, but...
AFDX (Avionics Full Duplex Switch Ethernet) is an aviation data bus, which is developed on the basis of Ethernet. Whether the data communication is deterministic concerns the airworthiness of AFDX, so this paper discusses the end-to-end delay in AFDX network especially the switch latency. To a great extent, the delay characteristic of the AFDX switch affects the determination of network transmission...
This paper deals with a precise time, particularly comparison of diverse precise time transfer methods and sources. We deal with two ways of the precise time acquisition — the dedicated time and frequency transfer infrastructure and the time network protocols. For the needs of distinct time and frequency methods evaluation, we designed a FPGA based System on Chip (SoC) that may acquire time and frequency...
The rapid growth of wire RC delay with technology scaling has put increasing pressure on FPGA architects to make more efficient use of the different layers available in the metal stack. While commercial FPGA architectures have implemented the majority of inter-logic-block wiring on the lower metal layers and a small fraction of wires on the least-resistive upper metal layers, published explorations...
This article present the design of automatic component to control room condition. The lights and fan will turn on in accordance ideal temperature workspace when there are peoples in the room and if no one in the room then the room lights and fan will not be active. This research use PIR sensor and LM35 as input, a component is developed based on FPGA device. The IP core of component is ready to fabricate,...
This paper presents the design of a hardware simulator for Multiple-Input Multiple-Output (MIMO) cooperative time-varying propagation channels with heterogeneous systems. The simulator reproduces a desired radio channel environment and makes it possible to test "on table" different systems. A specific architecture of the simulator digital block is presented to characterize outdoor/outdoor-toindoor/indoor...
The purpose of this paper is to present the digital overcurrent detector for the peak current mode dc-dc converter which has been already applied to the server for the data center. The proposed peak current detection circuit is composed of the RC integrator and comparator as the A-D converter for the detected current. The proposed method can detect the overcurrent by using the RC integration time...
Despite the perceived lightweight and structural regularity of Arbiter PUF (APUF), high quality (bias -- free) large APUF implementation on FPGA has traditionally proved to be challenging. Currently, the most widely accepted design approach for FPGA -- based APUF implementation is the Programmable Delay Line (PDL) based APUF. In this work, we describe a scalable design methodology to implement close-to-ideal...
In this paper we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Trees (MoT) topology for FPGA architecture design. To obtain the optimal MoT-based interconnect structure, the routing architecture of the 2D MoT-based FPGA is modified to include long routing segments that span multiple switch blocks in every row and column. By adjusting the percentage...
A wave-pipeline is a design technique for achieving high-speed and low-power operations also in field-programmable gate arrays (FPGAs). It realizes pipeline operations by adjusting delay times. Implementation of fine-tuning of wave-pipelines is possible to further increase the throughput. However, in the FPGA, it is not able to be executed by the restriction on the structure. This paper proposes a...
The communication between processing elements are suffering challenges due to latency. The arbitration algorithm used inside an arbitration unit of a network-on-chip based router plays a significant role in determining the performance of the whole network-on-chip based mesh. This paper revaluates some of the standard forms of the arbitration algorithms and presents the synthesis and implementation...
As device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits. One possible approach to this growing problem is to add redundancy to propose defect-tolerant architectures. But, hardware redundancy increases area. In this paper, we propose a method to determine the most critical elements...
The Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential Logic (WDDL) on a custom tree-based FPGA of 2048 cells. The WDDL technique offers an effective way to...
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