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A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against...
In this paper we use a 4-bit carry look-ahead adder to highlight the contribution by false-starts (glitches) to overall dynamic power dissipation. These false-starts occur in the generation of the sum outputs and are due to delays in generating and propagating the carry signals. We employ sub-threshold transistor operation in the none critical path and reduce power dissipation by 40%. Post layout...
The Quantum-dot cellular automate (QCA) approach is a promising nanotechnology and an alternative for current CMOS technology. It is an appropriate method for the design of high speed and low power digital circuits. Multipliers are used a lot for arithmetic operations in signal, image processing and scientific applications. This paper focuses on efficient design of QCA-based FIR serial multipliers...
The addition is the most used arithmetic operation in Digital Signal Processing (DSP) algorithms, such as filters, transforms and predictions. These algorithms are increasingly present in audio and video processing of battery-powered mobile devices having, therefore, energy constraints. In the context of addition operation, the efficient 4-2 adder compressor is capable to performs four additions simultaneously...
The Parallel Self Timed adder (PASTA) is based on a recursive formulation for performing multi bit binary addition. The operation is parallel for those bits and do not need any of the carry chain propagation. The main objective of this paper is to reduce the power consumption and also to increase the performance. The existing design attains good performance over random operand conditions without any...
A full adder circuit is considered as one of the basic building blocks of Digital Signal Processors (DSPs), Arithmetic and Logic Units (ALUs), Application Specific Integrated Circuits (ASICs) and many other digital circuits and systems. Today, efficient full adder circuit design is one of the main challenges for VLSI engineers. This paper proposes a novel 1-bit full adder circuit designed using N-MOS...
In general, Decimal adder has significant importance in arithmetic circuits for decimal addition. In the near future, high density arithmetic circuits can be achieved with the advantage of the small size of dots in QCA. Quantum - dot Cellular Automata (QCA) is an emerging approach for nano devices to construct the digital circuits. This paper presents a new correction logic for single-digit BCD adder...
This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“Vdd”) down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80...
Digital multiplier and squarer circuits are indispensable in Digital signal processing and cryptography. In many mathematical computations, squaring and cubing are frequently used. Generally the multiplier is used in computing square. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage...
Multipliers are key components of many high performance systems such as FIR filters, microprocessors, digital signal processors, etc. A system's performance is generally determined by the performance of the multiplier as the multiplier is generally the slowest element in the system. The analysis of performance parameters of different multiplier logics is essential for design of a system intended for...
Ling-carry adders that use a Ladner-Fischer parallel-prefix algorithm for carry computation are explored for quantum-dot cellular automata (QCA) nanotechnology implementations. The results derived from drawn layouts, indicate that the proposed adders outperform in terms of delay all previously reported architectures explored for QCA implementations. The delay difference is becoming bigger in favor...
Low-power circuits are becoming more attractive due to growing of portable device markets. The 1-bit full adder cell is the key building block for any ASIC design. Designing of such low power full-adder circuits is always a challenging concern for any design research. In this paper, we present a new full-adder cell which is designed with multiple pass transistor logic styles, in which some of them...
This paper explores the design of parallel multipliers for Quantum-Dot Cellular Automata. Array multipliers, Wallace multipliers, Dadda multipliers, and quasi-modular multipliers are designed and analyzed. Quasi-modular multipliers use 4 (n/2 × n/2) modules to make n × n multipliers are also considered. All of these designs are constructed using coplanar layouts. The delay, area and complexity are...
Traditionally, the minimum possible area of a very large scale integration (VLSI) layout is considered to be the best for delay and power minimization due to decreased interconnect capacitance. This paper, however, shows that the use of minimum area does not result in minimum power and/or delay in nanometer-scale technologies due to thermal effects and, in some cases, may cause thermal runaway. A...
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