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Multipliers are core components of most of the digital signal processing algorithms which lie in critical delay path and decide performance of any algorithm. Over the years various approaches have been proposed to reduce the computational overhead of conventional multipliers. Vedic mathematics has been one among them. In this paper, a novel multiplier unit is proposed which integrates the advantage...
CORDIC algorithm is suitable to implement sine/cosine function, but the large number of iterations lead to great delay and overhead. Moreover, due to finite bit-width of operands and number of iterations, the relative error of floating-point sine or cosine is terrible when the input angle is close to 0 or $\pi /2$ , respectively. To overcome these shortcomings, TCORDIC algorithm, which combines low...
Compressors form the basic element of arithmetic circuits that are dominated by multi-operand addition operations. Compressor circuits based on carry-save logic have been used in past to realize parallel multipliers for ASIC implementation, however, owing to the peculiar architecture of FPGAs, these circuits do not map well on these platforms. In this paper, FPGA implementation of 4:2 compressor circuit...
We propose a new approach to designing residue generators for an arbitrary moduli. Its novelty is that the carry-out bit is fed as multi-bit word back to the adder tree, while using reduction algorithms similar to the concepts of the compressor trees. For any modulus, reduction of multiple operands can be done using a carry-save adder (CSA) tree down to two vectors, which are then handled by an arbitrary...
During the design of embedded systems, many design decisions have to be made to trade off between conflicting objectives such as cost, performance, and power. Approximate computing allows to optimize each objective, yet for the sake of accuracy. This means that a functional flaw is allowed to produce an error as long as this is small enough to maintain a feasible operation of the system or guarantee...
The experimental metastability characterizationof a flip flop requires a controllable delay with low jitter andhigh time resolution. In FPGAs such an experiment can bevery useful for in-situ or even online characterization of agiven flip flop, but existing solutions rely on the availability ofa digital clock manager (DCM) or a phase locked loop (PLL) for implementing this controllable delay. Given...
Single-Event Effects are an increasingly important issue in electronic circuits due to technology scaling, efficient error detection schemes are thus required for circuits dedicated to radiative environments, such as in space applications. This work shows that the widespread spatial and temporal redundancy schemes exhibit widely different performances depending on technology, environment and circuit...
Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. This carry compression was implemented...
This paper presents architecture for a fused floating point three term adder unit. The fused or merge technique is described in this paper because in a fused technique three term addition is done in single unit. The purpose of doing this is to reduce delay, area as compared to traditional addition method. Several optimization techniques are used to reduce delay. The proposed design is implemented...
Standard wireless and mobile communication environments have huge demands on high speed signal processing operations. Finite Impulse Response (FIR) filter is one of the crucial factors in signal and image processing approaches. Traditional FIR filters have the advantage of linear phase, guaranteed stability, fewer finite precision errors and efficient implementation. However, they have a major disadvantage...
This paper presents the fast carry chain adder using Instantiation design entry which facilitates the direct design of the components through exact placement of the individual blocks in FPGA. The basic n-bit adder is divided into n/3 number of ripple carry adders with carry inputs generated from separate carry generator. The carry generator is designed on LUT by using all the six inputs with 100%...
Arithmetic adder is the most important basic element for many digital applications. In this paper different types of adders are taken for experimental study such as Ripple Carry Adder, Carry Save adder, Carry Look ahead adder, Carry Increment adder, Carry Select adder, and Carry Skip adder. Here in this paper introducing a novel technique for designing a new Carry Select adder for multi precision...
The proposed multiplier pertaining to concepts of Vedic Mathematics was designed to reduce propagation delay, design complexity as well as to optimize power consumption in comparison to conventional multipliers. A multiplier is a key element in DSP systems, serving as a building block of most computational digital systems, therefore, speed and power consumption are two important parameters of design...
Whilst the pre-fabricated aspects of FPGAs have many advantages, the fixed nature of the underlying fabric limits the optimized synthesis of arithmetic circuits on these platforms. Many adder architectures, that suit ASICs have been implemented using FPGAs and it has long been established that for FPGAs the ripple carry adder gives the best performance in terms of speed and resource utilization. This...
Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. However, one of the shortcomings of the existing flow lies in its inability to identify arithmetic operations when described as gate-level circuits...
Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Prior work on GPC synthesis using FPGAs has focused on utilizing the fast carry chain and mapping the logic onto LUTs. This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. Modern day Xilinx FPGAs support 6-input LUTs that can be used...
Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and...
A fixed-point ASIC design for high-speed, second-order, piecewise function approximation is presented. A Non-Uniform segmentation method based on Minimax approximation is used to get the interpolation coefficients. Non-Uniform segmentation, effectively, reduces the size of the coefficient table with a small area overhead for the address encoder. The proposed algorithm truncates the binary coefficients...
Fast multipliers are essential for many applications such as digital signal processing (DSP) and image and video processing. Tree parallel multipliers are the fastest ones. The only disadvantage of tree multipliers over serial multipliers is its high cost in terms of area and power dissipation. In this paper, we present a new efficient reduction scheme to implement tree multipliers on field programmable...
This study demonstrated a nonvolatile look-up table (nvLUT) that involves using resistive random access memory (ReRAM) cells with normally-off and instant-on functions for suppressing standby current. Compared with the conventional static random access memory (SRAM)-magnetoresistive random-access memory (MRAM)-hybrid LUTs the proposed ReRAM-based two-input nvLUT circuit decreases the number of transistors...
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