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In order to meet the demands for the high-density, high-performance, high-speed, smaller form factor and multi-function integration in portable electronic products, novel packaging technology now trends toward system in package (SiP) technology. 3D packaging technology is one of the most optimum means to achieve SiP. The embedded technology is one of the 3D packaging solutions and playing a key role...
Cure Induced Micro-Anomaly (CIMA) are worm like hollow microstructures found within resin rich region of underfill after curing within a BGA package with combination of copper die bumps and Sn-Ag substrate bumps. CIMA leads to solder extrusion during secondary reflow. Root cause of CIMA has been identified to be from thermal mechanical stress induced by the stiffness of the joints formed between the...
This paper presents the assembly optimization and characterization of through-silicon vias (TSV) interposer technology for two 8 ?? 10mm2 micro-bumped chips. The two micro-bumped chips represent different functional dies in a system-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100??m bump pitch and 1,124 I/O; the other micro-bumped chip had 50??m bump pitch and 13,413...
High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of...
As copper wire has excellent thermal conductivity, mechanical properties, low-cost advantages and copper stud bump process is similar the traditional wire bonding process, it makes copper stud bump technology better for medium and low I/O devices, and even in the future, it will expand into midrange I/O packages because it offers a large potential savings in packaging costs with the improved performance...
This paper presents new advancements in copper electroplating technology for both blind micro vias and through holes. Processes and manufacturing technology are described as well as current limitations and requirements. As a highlight the complete filling of through holes with electroplated copper by reversed pulse plating, RPP, is described. Both blind micro via and through hole filling using this...
This paper presents an investigation on field returned open and short failures related to printed circuit board (PCB), including via hole crack, prepreg crack and insufficient circuit etching. After an experimental study with cross section, time domain reflectometry (TDR), and finite element (FE) modelling, it was found that weak plating and corrosion induced via hole crack was a major root cause...
With the demands of miniaturized solutions that are able to handle increased heat dissipation, the use of silicon substrates with through-silicon vias (TSV) in electronics modules becomes more and more interesting. Shorter signal path, better cooling of tracks, better impedance control and smaller foot-prints are some of the advantages. This also avoids some RC delays of long, in-plane interconnects...
Radar sensors are already employed in production model vehicles e.g. for adaptive cruise control (ACC) systems. Further development of driver assistance systems has also led to the use of radar sensors in active safety systems (active brake assistance, collision warning, emergency braking, etc). However, the costs of manufacturing such radar-based systems, capable of gathering reliable information...
In this study, wafer level NCA patterning processes for CIS modules have been demonstrated and the effects of whole processes on NCAs were also investigated. At first, NCA solution was directly coated on a bumped wafer with Cu passivation on an image sensing area. Cu was sputtered on a NCA coated wafer, and then sputtered Cu layer was patterned using a photoresist lithography method. Subsequent NCA...
One promising application of CNTs in microelectronics is to use vertically aligned CNT (VACNT) arrays as novel thermal interface materials (TIMs). No doubt that the vertical alignment makes the best of the extremely high longitudinal thermal conductivity of individual CNTs; however, it is the CNT/substrate interface that exerts the main restriction on phonon transport through a TIM layer. There are...
PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch...
The demand for more complex and multifunctional microsystems with enhanced performance characteristics is driving the electronics industry toward the use of best-of- breed materials and device technologies. Three-dimensional (3-D) integration enables building such high performance microsystems through bonding and interconnection of individually optimized device layers. Bonding of device layers can...
In recent years, in order to achieve high density and high transmission speed between chips, various kinds of silicon modules have been developed. Our purpose is the development of silicon module in which several chips are mounted on the silicon substrate with Cu-Through Silicon Vias (Cu-TSVs) and fine multilayer Cu wirings such as global layer of devices. Since silicon substrate has a quite flat...
Portable products as well as some larger products may see failures by a high strain rate mechanical loading like that seen in a high or low level drop/shock event. Within the portable product industry there is a wide range of product design, usage and loading conditions. Because of this, standards such as JEDEC, which is meant to generate comparative results addressing component reliability, do little...
SiC power devices were die bonded to a AlN/Cu/Ni(Au) direct bonded copper (DBC) substrate with a Au-Ge eutectic solder in a vacuum reflow system. The long term joint reliability of the bonded chips was evaluated at 330degC in air for up to 1600 hours. The bonded samples were inspected with a micro focus X-ray TV system. The microstructure of the samples was observed and analyzed by the scanning electron...
In this work we modeled and simulated through silicon vias (TSV) in low, medium and high resistivity silicon (LRS, MRS and HRS) for frequencies up to 80 GHz. We then quantified the electromagnetic reliability (EMR) problems caused by conventional TSVs, in which silicon is used entirely as the medium for wave propagation. Our results revealed that using these conventional structures leads to high insertion...
In this paper the realization of packages and system-in-packages (SIP) with embedded components will be described. Embedding of semiconductor chips into substrates has several advantages. It allows a very high degree of miniaturization due to the possibility of sequentially stacking of multiple layers containing embedded components. A further advantage is the beneficial electrical performance by short...
Assembly of electronic components on rigid and/or flexible printed circuit boards is today the customary way to fabricate electronic systems in stationary, mobile and automotive applications. On the other hand, many of the demands from emerging application fields like wearable and textile electronics cannot be met if with standard technologies. These fields have therefore become mayor drivers for...
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