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PHP is the dominant server-side scripting language used to implement dynamic web content. Just-in-time compilation, as implemented in Facebook's state-of-the-art HipHopVM, helps mitigate the poor performance of PHP, but substantial overheads remain, especially for realistic, large-scale PHP applications. This paper analyzes such applications and shows that there is little opportunity for conventional...
Keypoint matching between images is an important technique for computer vision applications such as image retrieval. Although binary feature descriptors such as BRIEF enable fast measurement of distance, exhaustive search is still time-consuming. Hashing methods such as Locality Sensitive Hashing (LSH), while being effective to accelerate searching, result in large memory consumption and thus are...
This paper presents a novel radio-resource scheduler with a hardware accelerator for coordinated scheduling in 5G ultra-high-density distributed antenna systems. In 5G mobile communications systems, the transmission weight and the overall system throughputs for a huge number of possible combinations of antennas and user equipment have to be computed. To accelerate the scheduling, the new scheduler...
Hardware-software (HW-SW) partitioning plays a vital role in design phase of embedded system. The partitioning is a process to map each computation task in an application to either software or hardware. In general, hardware run faster compared to software, but with significant cost and resources utilization. Thus, current embedded system often incorporates a mix of hardware and software component...
Designing wireless industrial communication for factory automation is a serious task because novel radio systems have to compete with well established wired fieldbus solutions. The requirements to achieve equivalent reliability and latencies impose challenging demands on design and implementation. In this paper, we propose a hardware accelerator for highly adaptive and parallel medium access allowing...
Current handhelds incorporate a variety of acceler-ators/IPs for improving their performance and energy efficiency. While these IPs are extremely useful for accelerating parts of a computation, the CPU still expends a significant amount of time and energy in the overall execution. Coarse grain customized hardware of Android APIs and methods, though widely useful, is also not an option due to the high...
Real-time lossless compression can reduce the burden of big data transmission and storage. Hardware compression is faster and more energy saving when compared with software. This paper proposes a novel LZO hardware architecture and various acceleration methods, integrates the compressor module and other IP modules. Finally, test and demonstration are provided on the DE2 development board. The results...
Karatsuba Multiplication Algorithm is commonly used in modular multiplications of public-key cryptosystems with large key sizes. The overlapped summation in Karatsuba Multiplication is difficult for parallel acceleration in hardware implementations. This paper proposes a method of avoiding the overlapped summation under the circumstances of calculating Montgomery Modular Multiplication. The proposed...
All new Microsoft Azure and Bing servers are being deployed with an FPGA that sits both between the server and the data center network and on the PCIe bus. The FPGA is currently being used to accelerate networking on Azure machines and search on Bing machines, but could very quickly and easily be retargeted to other uses as needed. In this talk, I will describe how we decided on this architecture,...
Modern computer systems are accelerator-rich, equipped with many types of hardware accelerators to speed up computation. For example, graphics processing units (GPUs) are a type of accelerators that are widely employed to accelerate parallel workloads. In order to well utilize different accelerators to gain better execution time speedup or reduce total energy consumption, many scheduling algorithms...
Block traces are widely used for system studies, model verifications, and design analyses in both industry and academia. While such traces include detailed block access patterns, existing trace-driven research unfortunately often fails to find true-north due to a lack of runtime contexts such as user idle periods and system delays, which are fundamentally linked to the characteristics of target storage...
Large number addition is the fundamental operation in cryptography algorithms. In this paper, we accelerate large addition in hardware design by introducing non-least-positive form, which is beneficial to parallel processing. An implementation of 256-bit signed array accumulator with our method shows an improvement of 18% in speed and 15% in area-delay product compared with traditional design.
This study proposes a system-on-a-chip, field-programmable gate array (FPGA)-based real-time video processing platform for human action recognition. We provide the details of a hardware implementation for real-time human activity recognition in 3D scenes, including capture, processing, and display. The proposed platform is implemented by adding a two-stage preprocessing step to improve the results...
Aerial Robot is a new category of intelligent flying machines, which combines smart aerial platform with powerful sensoring and computation capability. Due to the high uncertainty and risk exiting in flight test, simulation is important in the development process. In this paper, we propose a simulation platform with dynamic scenario, based on the Robot Operating System (ROS) and Gazebo. Multiple moving...
Important design considerations for the cost-effective employment of hardware accelerators in next-generation data centers involve a) the type of candidate applications that a proposed solution can accelerate (generality), and b) the required development effort to successfully deploy the available accelerators for a given application (adoption overhead). To address the problem of generality, we present...
Iterative stencils are kernels in various application domains such as numerical simulations and medical imaging, that merit FPGA acceleration. The best architecture depends on many factors such as the target platform, off-chip memory bandwidth, problem size, and performance requirements. We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq...
In this paper, we present an FPGA hardware implementation approach for a phylogenetic tree reconstruction with maximum parsimony algorithm. The algorithm, based on stochastic local search, uses the Indirect Calculation of Tree Lengths and the Incremental Tree Optimization methods. We evaluate and compare our new approach against previous hardware approaches, and against TNT, the fastest available...
In this paper we present a framework for the seamlessly utilization of hardware accelerators in heterogeneous SoCs that are used to speedup the processing of Spark data analytics applications.
Reinforcement Learning (RL) is an area of machine learning in which an agent interacts with the environment by making sequential decisions. The agent receives reward from the environment to find an optimal policy that maximises the reward. Trust Region Policy Optimisation (TRPO) is a recent policy optimisation algorithm that achieves superior results in various RL benchmarks, but is computationally...
Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., regular expression evaluation, data analytics) or the data is less structured (e.g., text or long strings). With the increasing amount of user-generated data stored in relational databases, there...
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