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This paper proposes a new down-conversion method to attenuate leakage signal in frequency modulated continuous wave (FMCW) radar. The proposed method reduces the effect of phase noise in the leakage signal. It can be simply realized through digital signal processing without additional hardware. Specifications of practical FMCW radar and the phase noise which is bad enough were assumed and simulations...
FPGAs are becoming an attractive choice as a heterogeneous computing unit for scientific computing because FPGA vendors are adding floating-point-optimized architectures to their product lines. Additionally, high-level synthesis (HLS) tools such as Altera OpenCL SDK are emerging, which could potentially break the FPGA programming wall and provide a streamlined flow for domain experts in scientific...
As an alternative of adding more and more instructions to CPU cores in order to address a wide range of applications, this paper examines to use a mixed grained CPU interlay fabric to provide reconfigurable instruction set extensions. In detail, we are examining to replace the hardened NEON SIMD unit of an ARM Cortex-A9 with an identical sized FPGA fabric. We show that by applying a set of optimizations,...
Large number multiplication has always been an essential operation in cryptographic algorithms. In this paper, we propose Broken-Karatsuba multiplication by applying the non-least-positive form to represent large numbers and dig the parallelism hidden in conventional Karatsuba multiplication. Further, we modify Montgomery modular multiplication algorithm with Broken-Karatsuba multiplication to make...
The creators of the existing virtual museums of electronic technology (VIME) are mostly single enthusiasts. They pay the main attention to the technical exposition. In separate VIME there are also unique materials - interviews with the leaders of enterprises-manufacturers of equipment for different years. The design of machinery and the preparation of production is a "kitchen" for the creation...
Electrochemical Impedance Spectroscopy is widely popular in the medical field where it is often referred to as bioelectrical impedance analysis (BIA) used to analyze biological materials as well as characterization of body fluids. It is a complex technique requiring expensive equipment that is also large making it difficult to integrate into small form-factor systems that are hand-held, wearable and...
This work addresses the problem of estimating the accuracy of a certain class of digital signal processing algorithms, known as linear signal transforms, when implemented on field programmable gate array (FPGA) hardware computational structure (HCS) units. A solution is provided through the formulation of a hardware development framework which uses complex multipliers and complex addition units as...
In this paper, a high speed digital excess loop delay (ELD) compensation scheme with hybrid thermometer coding is proposed. In this high speed compensation, the time constraint of the DAC feedback route is shifted to the one clock compensation path. Also, the method to deal with the signal overflows the quantizer's range is analyzed. Compared to other digital ELD compensations, this scheme features...
Dynamic Partial Reconfiguration (DPR) can be used efficiently to implement a reconfigurable hardware platform for Software Defined Radio system that supports multiple wireless standards. This method optimizes several design metrics such as hardware resources, power, and reconfiguration time. Nevertheless, partitioning is a challengeable issue in the DPR flow. In this work, we implement two design...
FIR filter is significant unit in digital signal processing (DSP). In this paper a reconfigurable architecture named as modified constant shift method (MCSM) is proposed. The architecture uses the concept of compressors to make the FIR filter more power efficient. This compressor based adder-tree architecture is capable of working for different word lengths of FIR filter coefficient with less hardware...
The addition of hard blocks such as Block RAMs and Digital Signal Processors, have proven to be good means of improving various performance metrics in FPGAs. This however places stricter constraints on runtime relocation of hardware tasks and hence reduces their application in dealing with permanent faults. In this paper, we present a strategy that enhances the utilization of heterogeneous reconfigurable...
Our society relies upon information processing at a scale never seen before in human history. We are indeed experiencing an exponential growth in processing demand, as more and more applications in the most disparate domains emerge. While continuous improvements in the manufacturing processes of microprocessors has been able so far to mitigate the ecological and economical costs this trend imposes,...
We demonstrate real-time CD equalization (CDE) for coherent optical transmission systems using a low complexity time-domain (TD) multiplierless finite-impulse response (FIR)-based equalizer, based on a field-programmable gate array (FPGA) implementation. The real-time operation is performed for a single-channel 2.5 Gb/s QPSK optical signal with a performance penalty of only ∼0.15 dB with respect to...
A dynamic positioning controller based on the digital signal processor (DSP) is designed for certain crane vessel on the basis of the SRI-VC2110DP dynamic positioning system developed by Shanghai Ship and Shipping Research Institute. Based on the actual needs for the dynamic positioning controller, the hardware circuit consisting of dual CAN bus interface, dual Ethernet interface and I/O interface...
This paper proposes a novel method for performing division on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is based on an inverter, implemented as a combination of Parabolic Synthesis and second-degree interpolation, followed by a multiplier. It is implemented with and without pipeline stages individually and synthesized while targeting a Xilinx Ultrascale...
Parallel FIR filter is widely used among various types of filter in Digital Signal Processing (DSP). This paper shows the design of area-efficient 2-parallel FIR filter using VHDL and its implementation on FPGA using image system. This paper gives the details basic blocks of area-efficient 2-parallel FIR digital filter. In this paper proposed 2-parallel digital FIR filter and area-efficient 2-parallel...
Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing...
Analog-to-digital converters (ADC) in switching mode are used to convert the signals from multiple sources of the ADC means. It was considered appropriate, since it was believed that this provides a significant simplification of the hardware. Today, the advantage of hardware saving is negligible in compare with the loss of measurement accuracy because of the use of switching mode, which is unreasonably...
This paper presents a procedure to optimize modular multiplication by constants. Such operations have been demonstrated to be crucial to design efficient reverse converters, which are the bottleneck of RNS. The focus of this work is the use of Residue Number System (RNS) moduli sets without limitation of the number of channels, which are useful for Digital Signal Processing (DSP) applications. Moreover,...
Reconfigurable computing is rapidly establishing itself as a major discipline, involving the use of reconfigurable devices for computing purposes. This paper proposes the ORRes approach for a time-sharing of reconfigurable resources. We investigate the overlay architecture at the hardware layer to ensure the bitstream compatibility between heterogeneous FPGAs. Two novel overlay features are introduced:...
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