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This paper presents area-efficient building blocks for computing fast Fourier transform (FFT): multiplierless processing elements to be used for computing of radix-3 and radix-5 butterflies and reconfigurable processing element supporting mixed radix-2/3/4/5 FFT algorithms. The proposed processing elements are based on Wingorad Fourier transform algorithm. However, multiplication is performed by constant...
Advancements in deep learning have ignited an explosion of research on efficient hardware for embedded computer vision. Hardware vision acceleration, however, does not address the cost of capturing and processing the image data that feeds these algorithms. We examine the role of the image signal processing (ISP) pipeline in computer vision to identify opportunities to reduce computation and save energy...
This paper proposes a jumped matching depth estimation algorithm to calculate the disparity value in the 3D virtual view synthesis. The matching criterion adopts pixel value similarity, distance similarity and color information similarity as the weighted cost aggregation. In order to reduce the depth discontinuing and then providing the comfort of 3D watching, this paper proposes the disparity prediction...
This work addresses the problem of estimating the accuracy of a certain class of digital signal processing algorithms, known as linear signal transforms, when implemented on field programmable gate array (FPGA) hardware computational structure (HCS) units. A solution is provided through the formulation of a hardware development framework which uses complex multipliers and complex addition units as...
This brief presents the SoC-FPGA implementation of the modified Nearly Optimal Sparse Fast Fourier Transform (sFFT) algorithm. The implementation was carried out by using hardware/software co-design based on software profiling that helped to find out that pseudo-random Spectral Permutation, Windowing, and Sub-Sampling (SPWS) are the signal processing operations that require most processing time in...
A Sphere Decoder is a popular tree search algorithm for the solution of integer least squares minimisation problems. It has gained considerable attention for its application to maximum likelihood detection of digitally modulated signals in MIMO communication systems and can almost universally be applied to a plethora of problems with some modifications to the sphere constraint. This creates the need...
This paper presents a novel runtime-reconfigurable, mixed radix core for computation 2-, 3-, 4— point fast Fourier transforms (FFT). The proposed architecture is based on radix-3 Wingorad Fourier transform, however multiplication is performed by constant multiplication instead of general multiplier. The complexity is equal to multiplierless 3-point FFT in terms of adders/subtractors with the exception...
The proliferation of cyber physical systems in society, from the smart grid to sensor networks and robots has raised the importance of error resilience in signal processing and control systems to unprecedented levels. Resilience to errors in sensing and control algorithm execution in processors all the way down to circuits for sensing and actuation is of critical importance in safety-critical applications...
Using a new input restructuring sequence and an appropriate reordering of the elements involved, a new VLSI algorithm that uses short length pseudo-cycle convolution structures for the VLSI implementation of discrete sine transform is presented. It uses a new parallel decomposition of discrete sine transform (DST) that leads to a high throughput VLSI implementation with a low hardware cost. The proposed...
In this paper, we present a concept of a transistor level implementation of the Particle Swarm Optimization (PSO) algorithm that belongs to the group of unsupervised learning algorithms aimed at the design of artificial neural networks (ANNs). The algorithm exhibits an ability to search for an optimal solution in a multidimensional data space, in which many sub-optimal solutions may exist. The ANN...
Power hardware-in-the-loop modeling (PHIL) is one of advanced approach for test automation and verification of complex circuits and systems. This approach is most well used in power networks and power-trains. PHIL modeling is supposed part of a system is software model whether the other part is hardware item under test. A special interface algorithm supports interaction between computer model and...
This paper presents some work in progress on the development of fast and accurate support for complex floatingpoint arithmetic on embedded processors. Focusing on the case of multiplication, we describe algorithms and implementations for computing both the real and imaginary parts with high relative accuracy. We show that, in practice, such accuracy guarantees can be achieved with reasonable overhead...
The direct conversion (DC) architecture has been adopted for wireless base-station transceivers due to its cost and area efficiency. The shortcomings of DC transceivers need to be overcome to meet their high performance requirements. In-phase (I) and quadrature phase (Q) mismatch is one of most significant impairments. This paper presents an integrated, on-line mismatch compensation system which calibrates...
The estimation of sparse vectors is an important problem in digital signal processing. Recently, efficient iterative algorithms based on the so-called linearized Bregman iterations have been proposed, combining excellent estimation performance with low implementation complexity. Unfortunately, these algorithms typically use large numerical values, complicating fixed point implementations. To overcome...
This paper describes experience and lessons learned from teaching introductory Digital Signal Processing course as a part of Computer Engineering curricula using C based laboratory exercises. Matlab based laboratory exercises are substituted with a series of hands-on experiments which include implementation of signal processing algorithms using programing language C and DSP development boards, and...
One-bit transform method can be used for low computational complexity block based motion estimation with respect to hardware implementation in video coding systems. The principal of the one-bit transform method is based on kernel which has multi band pass filtering. In this work, the performance of the one-bit transform methods obtained with band pass filtering on the state of the art video coding...
In this paper, designing of stochastic multiplier and divider is proposed for designing of Lower-Upper decomposition (LUD) scheme. By using stochastic computation complicated operations of LUD can be performed by simple logic gates. By using stochastic multiplier and divider computational complexity is reduced. Stochastic multiplier and divider use the stochastic stream which reduces the computational...
In our demo, we present two hardware platforms for prototyping audio array signal processing. Pyramic is a 48-channel microphone array fitted on an FPGA and Compact Six is a portable microphone array with six microphones, closer to the technical constraints of consumer electronics. A browser based interface was developed that allows the user to interact with the audio stream from the arrays in real...
Multichannel active noise control (MCANC) systems are commonly used in acoustic noise or vibration control, such as large-dimension ventilation ducts, open windows and mechanical structures. However, its computational load far exceeds the capabilities of digital signal processors (DSPs) and microcontrollers. Even the field programmable gate array (FPGA) cannot straightforwardly cope with the exponential...
In this paper, we present a high speed yet energy efficient approximate divider where the division operation is performed by multiplying the dividend by the inverse of the divisor. In this structure, truncated value of the dividend is multiplied exactly (approximately) by the approximate inverse value of divisor. To assess the efficacy of the proposed divider, its design parameters are extracted and...
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