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In the evolving field of Internet of Things (IoT), wireless sensor networks serve as the backbone for data acquisition, processing, and transmission. Deployed sensor nodes are expected to communicate with one another, or with a base station. A new modulating scheme known as LoRa allows communication over long ranges but still consumes low power. One block that is needed to realize this is the analog-to-digital...
More than 80% of the 1.2 billion individuals without electricity live in rural regions of developing countries. For many of these communities, electricity access through the traditional paradigm of power infrastructure growth, increasing generation capacity of centralized grids and installing capital intensive transmission lines, substations, and distribution lines, will be financially infeasible...
The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without...
A low-voltage, ultra-low power sensor interface for electromyogram (EMG) signal acquisition is presented. The sensor interface consists of an amplifier and a SAR ADC that work from a 0.3V supply. The low-voltage amplifier topology provides a noise level of 26μVrms, 40dB gain and a state-of the art power efficiency factor (PEF) of 2.2 from a 20–425Hz bandwidth. Low-voltage supply improves the power...
Network-on-Chip (NoC) has been proposed as an interconnection framework for connecting large number of cores for a System-on-Chip (SoC). Assuming a mesh-based NoC, we explore the assignment of cores to cross-points and produce a best NoC configuration with minimum average communication traffic, power consumption and chip area. We use pre-synthesized network components data to estimate power and chip...
Interfacing techniques for near-threshold computing are described in this paper. A bi-directional input/output circuit with integrated level shifters is proposed for multiple near-threshold power domains. The circuit provides conversion ranges of 0.38 V to 1.2 V and 0.45 V to 3.3 V depending on the targeted output voltage. Eight different configurations of I/O circuits are evaluated with level shifters...
This paper presents an overview of the design considerations and challenges of event-driven wakeup receivers as well as an analysis of state-of-the-art (SOA) research. We consider advantages and disadvantages of the commonly utilized architectures in these systems as well as presenting big picture perspectives from an application standpoint. This paper focuses on event-driven scenarios where the activity...
The literature presents many different active pixel sensor (APS) topologies operating in the high dynamic range logarithmic mode, as well as, different techniques to improve image quality by attenuating fixed-pattern noise (FPN). Together with the proposed solution, the advantages and disadvantages of each new solution are usually presented in their published reports. However, it is hard to find different...
Aggregation of behind-the-meter distributed energy resources holds promise to provide valuable services to the grid, enabling greater penetration of intermittent renewable energy sources. We propose the Smart Dim Fuse system as an approach to utilize loads for aggregation services. The Smart Dim Fuse, installed on individual circuits at the breaker panel, enables load power control without service...
This paper aims to quantitatively measure the impact of different data centers networking topologies on the performance and energy efficiency of shuffling operations in MapReduce. Mixed Integer Linear Programming (MILP) models are utilized to optimize the shuffling in several data center topologies with electronic, hybrid, and all-optical switching while maximizing the throughput and reducing the...
In this paper, a novel 10 bit 20 MS/s, low power, pipelined ADC using both capacitor and opamp sharing techniques is proposed. In the proposed ADC, feedback capacitors in the first four stages are shared between adjacent stages in order to decrease the power dissipation of the opamps used in these stages. The opamps in the six pipeline stages are also shared between adjacent stages in pairs for further...
In this paper, we propose a three-stage reconfigurable topology synthesis approach for Application-Specific NoC (ASNoC) on partially dynamically reconfigurable FPGAs, where the topology is reconfigured dynamically at run-time along with the application’s execution. Firstly, given the scheduling and floorplanning of task modules, an Integral Linear Programming (ILP)-based method is proposed to partition...
A novel pixel architecture for CMOS image sensors is presented. It uses only one amplifier for both integration of the photocurrent and in-pixel noise cancelation, thus minimizing power consumption. The circuit is specifically designed to be used in readout systems for lateral flow immunoassays. In addition a switching technique is introduced enabling the use of column correlated double sampling technique...
Fifth generation (5G) wireless networks will target at energy and spectrum efficient solutions to cope with the increasing demands in capacity and energy efficiency. To achieve this joint goal, dense networks of small cells (SCs) are expected to overlay the existing macro cells. In parallel, for the SC connection to the core network, a promising solution lies in a mesh network of high capacity millimeter...
This paper carries out a power-driven performance analysis on the most widely used LC oscillators' topologies, by means of the Inversion Coefficient methodology. The aim is to investigate on the best trade-off for Internet-of-Things related applications, where power consumption shall be minimized. The analysis is based on the BSIM6 model targeting a 40nm CMOS technology to investigate the trade-offs...
This paper presents a complete family of integrate- and-fire modulator (IAF) topologies to improve in-pixel signal linearity in digital imagers. Three types of soft-reset schemes are analyzed for capacitive trans-impedance amplifiers (CTIAs). The proposed Type III has the main advantages of avoiding any low-impedance voltage source or extra capacitor, of including correlated double sampling (CDS)...
The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption...
This paper presents a capacitively-coupled chopper instrumentation amplifier (CCIA) for portable EEG detection devices. In this design, the current-reuse technology is adopted in the core amplifier and the ripple reduction loop (RRL) to cut down the power consumption of the whole system. A novel ripple reduction loop based on ping-pong auto-zeroing topology is proposed to reduce the ripple at the...
Datacenter networks (DCNs) play an important role in supporting cloud computing and Internet-based services. The cost and power consumption of a DCN grow rapidly with the increases of network scale and bandwidth requirement. The cost, complexity and efficiency of a DCN are determined by several design factors including the topology, addressing and routing. In this paper, we propose a simple and cost-effective...
Wireless Sensors Networks (WSN) have become vital in many areas and critical applications. Some applications require a reliable network and less maintenance, especially the power consumption. ZigBee standard shows the ability to be used for many applications that require low data transmission and low power consumption. The standard helps the overall network to reduce worries about the sensors power...
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