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In cloud storage systems, the use of erasure coding results in high read latency and long recovery time when drive or node failure happens. In this paper, we design a parity independent array codes (PIT), a variation of STAR code, which is triple fault tolerant and nearly space-optimal, and also propose an efficient single-failure recovery scheme (PITR) for them to mitigate the problem. In addition,...
A 4 kb fully differential 8-port SRAM bitcell array (6 read ports and 2 write ports) is presented in this paper. This 8-port SRAM provides simultaneous access, high system throughput and a great read static noise margin by isolating the read ports from storage nodes. At 0.4 V supply voltage, designed 8-port SRAM bitcell shows 123, 137 and 123 mV static noise margin during read, write and standby modes,...
The extremely strict code length constraint is the main drawback of lowest density, maximum-distance separable (MDS) array codes of distance greater than 3. To break away from the status quo, we proposed in [5] a family of lowest density MDS array codes of (column) distance 4, called XI-Code. Compared with the previous alternatives, XI-Code has lower encoding and decoding complexities, and much looser...
A decoding algorithm is presented for rank-metric array codes that are based on diagonal interleaving of MDS codes. W.r.t. this metric, such array codes are known to be optimal when the underlying field is algebraically closed. It is also shown that for any list decoding radius that is smaller than the minimum rank distance, the list size can be bounded from above by an expression that is independent...
With the rapid proliferation of camera-equipped smart device, two dimensional barcode obtains the widespread application in daily life. Embeding URL information to a barcode becomes popular and convenient. There is increased interest in the use of color barcode to encode more information than regular black-and-white barcode. This paper presents CodeCube-a multi layer color barcode for mobile society...
In recent years, the demand for memory performance has grown rapidly due to the increasing number of cores on a single CPU, along with the integration of graphics processing units and other accelerators. Caching has been a very effective way to relieve bandwidth demand and to reduce average memory latency. As shown by the cache feature table in Fig. 23.9.1, there is a big latency gap between SRAM...
Smart home environment is typically comprised of two parts: a home gateway and a number of home appliances. One of the challenges faced by ZigBee is its resource-efficient firmware update. A commonly used method is to compress the firmware before sending it to the ZigBee end nodes. The receiver side, i.e., the ZigBee end nodes, have limited resources in terms of storage and communication bandwidth...
QR i.e. "Quick Response" code is a 2D matrix code that is designed by keeping two points under consideration, i.e. it must store large amount of data as compared to 1D barcodes and it must be decoded at high speed using any handheld device like phones. QR code provides high data storage capacity, fast scanning, omnidirectional readability, and many other advantages including, error-correction...
Burst error occurs due to various factors and degrades the system performance. In this paper, we propose a burst error sensing scheme for page-oriented data. Using this scheme, the proposed method can sense a two-dimensional burst error location. In addition, it is possible to improve the performance by using erasure decoding on the sensed burst error position.
The systematic polar codes under successive cancellation list (SCL) decoding suffers from very high time and space complexity when list size becomes larger. Aimed at getting the tradeoff between error performance and algorithm complexity, a practical CRCs-ADSCL(Adaptive SCL) decoding scheme is proposed for systematic polar codes, in which CRC values will be held by the bit-pair arrays in the decoding...
A 6-bit pseudo segmented current-steering digital-to-analog converter (DAC) designed in 40nm low-leakage (LL) CMOS process is presented. The DAC employs 4× time-interleaved (TI) topology which enables sampling rates up to 16GS/s with relatively low clock frequency. A design-for-test on-chip memory with 6bits1-k bytes/bit is programmed with strictly costumed data sequence and read out at 1Gb/s rate,...
An energy-efficient analog SRAM (A-SRAM) is proposed to eliminate redundant analog-to-digital (A/D) and digital-to-analog (D/A) conversions in the mixed-signal processing such as a biomedical and a neural network applications. The D/A and the A/D conversion are integrated into the SRAM readout by the charge sharing of the proposed split bit-line (BL) and the SRAM write by the successive approximation...
Channel coding and information theoretic approaches have been utilized in conventional non-volatile memories to overcome their inherent design limitations of leakage, coupling and refresh rates. However, the continuous scaling and integration constraints set on the current devices directed the attention towards emerging memory technologies as suitable alternatives. Memristive devices are prominent...
In this paper, we explore different techniques for lossless compression of sensor data on a wireless sensor network. In this work, we applied modify Differential Pulse Code Modulation (DPCM) scheme for our baseline lossless compression. These techniques were applied on sensor types with reasonably predictable data pattern (e.g., temperature sensor, pressure sensor, etc.) allowing about 50% data compression...
Computer systems research is often inhibited by the availability of memory designs. Existing Process Design Kits (PDKs) frequently lack memory compilers, while expensive commercial solutions only provide memory models with immutable cells, limited configurations, and restrictive licenses. Manually creating memories can be time consuming and tedious and the designs are usually inflexible. This paper...
Emerging resistive random-access memory (RRAM) can provide non-volatile memory storage but also intrinsic logic for matrix-vector multiplication, which is ideal for low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM-based computing device is mainly assumed on a multi-level analog computing, whose result is sensitive to process non-uniformity as...
Side channel attacks exploit inadvertent information leakage from the physical implementation of computing systems, bypassing the theoretical strength of cryptographic algorithms. Of particular concern are software side-channel attacks which can be mounted remotely without access or alteration of the hardware system. One type of attack that has been demonstrated to be highly effective is cache timing...
Bloom filters are used in many computing and networking applications where they provide a simple method to test if an element is present in a set. In some of those systems, reliability is a major concern and therefore the Bloom filters should be protected to ensure that errors do not affect the system behavior. One of the most common type of errors in electronic implementations of Bloom filters are...
We consider a window decoding scheme for Braided Convolutional Codes (BCCs) based on the BCJR algorithm. We describe the principle of this decoding scheme and show that BCCs with window decoding exhibit excellent performance. The tradeoff between performance and decoding latency is examined and, to reduce decoding complexity, both uniform and nonuniform message passing schedules within the decoding...
Implementing last level caches (LLCs) with STT-MRAM is a promising approach for designing energy efficient microprocessors due to high density and low leakage power of its memory cells. However, peripheral circuits of an STT-MRAM cache still suffer from leakage power because large and leaky transistors are required to drive large write current to STT-MRAM element. To overcome this problem, we propose...
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