The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Routing algorithms can improve network performance by maximizing routing adaptiveness but can be problematic in the presence of endpoint congestion. Tree-saturation is a well-known behavior caused by endpoint congestion. Adaptive routing can, however, spread the congestion and result in thick branches of the congestion tree — creating Head-of-Line (HoL) blocking and degrading performance. In this...
Simulation is one of the main tools used to analyze new proposals in the Network-on-Chip (NoC) field. Among these simulators for analyzing and testing new ideas in NoC architectures, the Noxim simulator stands out, being used by many researchers due to the wireless support and open-source availability. An important issue at the simulation phase is the choice of workload, as it may affect testing the...
Digital circuit technologies at nanoscale levels increase the likelihood of permanent, transient and intermittent faults. As a result, the demand for fault tolerance strategies is the main subject of many types of research targeting System-on-Chip (SoC) designs. In particular, retransmission mechanisms are one of the most used solutions in the Network-on-Chip (NoC) operation, but these mechanisms...
As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip...
Aèsiraci-Networks-on-Chip are vulnerable to a variety of manufacturing and design factors making them susceptible to disparate faults that cause corrupted message transfer or even catastrophic system failures, due to the central position of the NoC in the system. Therefore, a NoC system should be fault-tolerant to transient malfunctions or permanent physical damages. The terminology of fault tolerant...
CPU-GPU heterogeneous systems are emerging are emerging as architectures of choice for high-performance energy-efficient computing. Designing on-chip interconnects for such systems is challenging: CPUs typically benefit greatly from optimizations that reduce latency, but rarely saturate bandwidth or queueing resources. In contrast, GPUs generate intense traffic that produces local congestion, harming...
A novel Denial-of-Service attack for Networks-on-Chip, namely illegal packet request attack (IPRA), has been proposed and measures to mitigate the same have been addressed. Hardware Trojans, which cause these attacks, are conditionally triggered inside the routers at the buffer sites associated with local core, when the core is idle. These attacks contribute to the degradation of network performance...
Routing algorithms play an important role in Network-on-Chip (NoC) based System-on-Chips. Turn model based routing disallows some of the turns in order to avoid deadlock, while providing partial adaptivity. In this paper, all 2D uniform turn models are examined for deadlock freeness and connectivity; 50 deadlock free turn models are extracted that provide full connectivity in the network. An extended...
As the development of processors/SoCs (System-on-Chips), NoC (Network-on-Chip) consumes an increasing fraction of the modern processors/SoCs power. Thus, designing energy-efficient NoC architecture is imperative. Multi-NoC (Multiple Network-on-Chip) behaves well in power gating for reducing leakage power, which constitutes a significant fraction of NoC power. In this paper, we propose CRA, a novel...
3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. In addition, the number of vertical paths can be expected to be...
Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the Network-on-Chip (NoC) paradigm has emerged to address the scalability and performance shortcomings of bus-based interconnects. As the feature size shrinks, the system gets much more susceptible to faults caused by wear-out and environmental effects...
Designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implementation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. This paper proposes the...
The NoC Architecture plays crucial role while designing communication systems for System on Chip (SoC). The NoC architecture is improved over conventional bus, shared bus design and cross bar interconnection architecture for on chip networks. In order to improve the Quality of Service, Congestion, Throughput and latency in NoC, Hexagonal node based architecture is proposed in our previous paper[14]...
With NoCs (Networks-on-Chips) becoming a central part of today's many-core systems, ensuring a good level of performance at the routing level has never been so crucial. In previous works, we have introduced a novel method for designing fully adaptive deadlock-free routing algorithms for NoCs called ESPADA (EScape PAths with Dynamic channel Acquisition). The strength of our approach lies in its ability...
Communications systems make heavy use of FPGAs; their programmability allows system designers to keep up with emerging protocols and their high-speed transceivers enable high bandwidth designs. While FPGAs are extensively used for packet parsing, inspection and classification, they have seen less use as the switch fabric between network ports. However, recent work has proposed embedding a network-on-chip...
Multi-FPGA platforms are considered to be the most appropriate experimental way to emulate a large Multi-Processor System-on-Chip based on a Network-on-Chip. However, the use of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links between routers. As the ratio of the logic capacity to the number of IOs only increases slowly with each generation of...
Conventional fault-tolerance approaches for Networks-on-Chip (NoCs) cannot be applied to high assurance real-time systems due to their different goals and constraints. These systems impose strict integrity, resilience and real-time requirements. All possible effects of hardware errors must be taken into account and the resulting system must be predictable, even in the presence of errors. In this paper,...
Network-on-Chip (NoC) based systems are becoming more acceptable nowadays compared to System-on-Chips (SoC) for nanoscale system development due to increasing scaling. The weakness of wired communication leads to insertion of wireless links in NoC Systems to mitigate the multihop problem. Present work provides significant improvements of NoC and Wireless NoC (WNoCs) systems contributing salient techniques...
In this paper, we propose a model along with a novel methodology to represent and validate a Network-On-Chip (NoC) server processor's Reliability, Availability, and Serviceability (RAS) functions during the pre-silicon design phase. The effectiveness of this methodology is demonstrated in a real-life use case on one of the most advanced NoC Server designs in the industry.
Table-based routing is a common approach for a fault-tolerant Network-on-Chip (NoC). This approach is hard to scale, since the table size tends to grow according to the NoC size. To surpass this problem, some works, such as the Region-Based Routing (RBR), have proposed techniques for saving routing tables area. This work proposes an alternative routing technique finding among communication pairs selected...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.