Search results for: Farzan Jazaeri

Items from 1 to 20 out of 21 results

article

Charge-Based Modeling of Radiation Damage in Symmetric Double-Gate MOSFETs

Farzan Jazaeri, Chun-Min Zhang, Alessandro Pezzotta, Christian Enz

IEEE Journal of the Electron Devices Society > 2018 > 6 > 1 > 85 - 94

In this paper, a comprehensive charge-based predictive model of interface and oxide trapped charges in undoped symmetric long-channel double-gate MOSFETs is developed. The model involves essentially no fitting parameters, but first-principle calculations of both oxide and Si/oxide interface trapping. This charge-based approach represents an essential step toward compact modeling of ionizing dose and...

article

Free Carrier Mobility Extraction in FETs

Farzan Jazaeri, Alessandro Pezzotta, Christian Enz

IEEE Transactions on Electron Devices > 2017 > 64 > 12 > 5279 - 5283

In this paper, we propose an accurate method to extract the free carrier mobility in field effect transistors. This derivation relies only on the drift-diffusion transport model without the need to predefine the gate-voltage-mobility dependence. This approach has been assessed with technology computer-aided design simulations, confirming its robustness even in the presence of short-channel effects...

article

Characterization of GigaRad Total Ionizing Dose and Annealing Effects on 28-nm Bulk MOSFETs

Chun-Min Zhang, Farzan Jazaeri, Alessandro Pezzotta, Claudio Bruschini, more

IEEE Transactions on Nuclear Science > 2017 > 64 > 10 > 2639 - 2647

This paper investigates the radiation tolerance of 28-nm bulk

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and

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MOSFETs up to 1 Grad of total ionizing dose (TID). The radiation effects on this commercial 28-nm bulk CMOS process demonstrate a strong geometry dependence as a result of the complex interplay of oxide and interface charge trapping relevant to the gate-related dielectrics and the shallow trench isolation. The narrowest/longest...

article

Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

Ali Saeidi, Farzan Jazaeri, Francesco Bellando, Igor Stolichnov, more

IEEE Electron Device Letters > 2017 > 38 > 10 > 1485 - 1488

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs...

chapter

Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation

Ali Saeidi, Farzan Jazaeri, Francesco Bellando, Igor Stolichnov, more

2017 47th European Solid-State Device Research Conference (ESSDERC) > 78 - 81

ESSDERC 2017 - 47th IEEE European Solid-State Device Research Conference (ESSDERC)

This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative capacitance effect. In hysteretic devices, subthreshold slope as steep as 10mV/dec is achieved in the region where the ferroelectric represents an...

chapter

Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing

Arnout Beckers, Farzan Jazaeri, Andrea Ruffino, Claudio Bruschini, more

2017 47th European Solid-State Device Research Conference (ESSDERC) > 62 - 65

ESSDERC 2017 - 47th IEEE European Solid-State Device Research Conference (ESSDERC)

This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters...

chapter

Variability of Low Frequency Noise and mismatch in CORNER DOPED and standard CMOS technology

Mathieu Coustans, Farzan Jazaeri, Christian Enz, Francois Krummenacher, more

2017 International Conference on Noise and Fluctuations (ICNF) > 1 - 4

2017 International Conference on Noise and Fluctuations (ICNF)

Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is a main concern in analog CMOS integrated circuits. For instance circuits such as current reference, SRAM, ring oscillators are ultimately limited by noise level and mismatch. In this work, CORNER DOPED devices have been fabricated, measured, and finally compared with standard CMOS technology with particular emphasis on weak...

article

Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Ali Saeidi, Farzan Jazaeri, Igor Stolichnov, Adrian M. Ionescu

IEEE Transactions on Electron Devices > 2016 > 63 > 12 > 4678 - 4684

In this paper, we propose and investigate the high-performance and low-power design space of nonhysteretic negative capacitance (NC) MOSFETs for the 14-nm node based on the calibrated simulations using an experimental gate-stack with PZT ferroelectric to obtain the NC effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure...

article

Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

Ashkhen Yesayan, Farzan Jazaeri, Jean-Michel Sallese

IEEE Transactions on Electron Devices > 2016 > 63 > 3 > 1368 - 1374

Nanowire (NW) semiconductors are interesting devices for being used as sensors. Such NWs are doped silicon channels with electrical contacts at both ends, which is a kind of the so-called junctionless (JL) device. However, in contrast with the state-of-the-art CMOS FETs, a relatively high concentration of traps is expected when using these architectures as biosensors, since their surface is supposed...

article

Carrier Mobility Extraction Methodology in Junctionless and Inversion-Mode FETs

Farzan Jazaeri, Jean-Michel Sallese

IEEE Transactions on Electron Devices > 2015 > 62 > 10 > 3373 - 3378

In this paper, we propose a new method to extract the free carrier mobility in junctionless (JL) double-gate FETs biased in accumulation. We show that, in addition to assuming a well-defined field-dependent mobility law, using the well-known

$Y$

-function is not accurate enough in JL FETs. In addition, the new methodology is also interesting for inversion-mode FETs. This approach has been assessed...

article

Modeling Channel Thermal Noise and Induced Gate Noise in Junctionless FETs

Farzan Jazaeri, Jean-Michel Sallese

IEEE Transactions on Electron Devices > 2015 > 62 > 8 > 2593 - 2597

This paper presents analytical expressions for channel noise, induced gate noise (IGN), and cross-correlation noise in a long-channel junctionless (JL) double-gate MOSFET. The analytical relationships, which have been derived from a coherent charge-based model, are validated with technology computer-aided design simulations, and the figures of merit have been compared with the inversion mode FETs...

chapter

FOSS EKV 2.6 parameter extractor

Wladek Grabinski, Daniel Tomaszewski, Farzan Jazaeri, Anurag Mangla, more

2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES) > 181 - 186

2015 MIXDES - 22nd International Conference "Mixed Design of Integrated Circuits & Systems"

The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS technologies continue geometry scaling the designers can benefit using dedicated SPICE MOSFET models and apply specific analog design methodologies. The...

article

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

Lucian Barbut, Farzan Jazaeri, Didier Bouvet, Jean-Michel Sallese

IEEE Transactions on Electron Devices > 2014 > 61 > 7 > 2486 - 2494

This paper investigates a new method to measure mobility in nanowires. With a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low-dimensional structures such as nanowires may generate large errors, while being challenging from a technological aspect. Here, we propose to extract the drift mobility in nanowires by...

article

Generalized Charge-Based Model of Double-Gate Junctionless FETs, Including Inversion

Farzan Jazaeri, Lucian Barbut, Jean-Michel Sallese

IEEE Transactions on Electron Devices > 2014 > 61 > 10 > 3553 - 3557

In this brief, we have developed a charge-based model for the symmetric double-gate junctionless (JL) field effect transistor (FET) that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a former model and aims at giving a unified description of JL FETs beyond the domain of operation for which they have...

article

Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

Farzan Jazaeri, Lucian Barbut, Jean-Michel Sallese

IEEE Transactions on Electron Devices > 2014 > 61 > 12 > 3962 - 3970

This paper aims to model asymmetric operation in double-gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concept. In addition to the benefits in terms of compactness and coherence, such equivalence is used to develop a complete charge-based model for independent...

chapter

Design space of twin gate junctionless vertical slit field effect transistors

Lucian Barbut, Farzan Jazaeri, Didier Bouvet, Jean-Michel Sallese

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013 > 393 - 396

2013 MIXDES - 20th International Conference "Mixed Design of Integrated Circuits & Systems"

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters. This work could serve as a guideline for technology...

chapter

Heavily doped junctionless vertical slit FETs with slit width Below 20 nm

Lucian Barbut, Farzan Jazaeri, Didier Bouvet, Jean-Michel Sallese

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013 > 397 - 400

2013 MIXDES - 20th International Conference "Mixed Design of Integrated Circuits & Systems"

This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×10¹⁸ atoms/cm³. The devices demonstrate up to six decades of I_on/I_off ratio and a sub-threshold swing of 90 mV/decade relative to a slit width of approximately 10 nm.

article

A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut, Nicolas Chevillon, more

IEEE Transactions on Electron Devices > 2013 > 60 > 12 > 4277 - 4280

In this paper, we evidence the link between the planar and cylindrical junctionless field effect transistors (JL-FETs) from the electrostatics and current point of view. In particular, we show that an approximate solution of the Poisson–Boltzmann equation for JL nanowires can be mapped on the planar double-gate topology generating only negligible mismatch, meaning that both devices can share the same...

article

Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

Farzan Jazaeri, Lucian Barbut, Jean-Michel Sallese

IEEE Transactions on Electron Devices > 2013 > 60 > 7 > 2120 - 2127

In this paper, we investigate the technological constrains and design limitations of ultrathin body junctionless double gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of OFF-state-current and voltages are obtained and validated with TCAD simulations. This set of analytical expressions can be used as...

article

Trans-Capacitance Modeling in Junctionless Symmetric Double-Gate MOSFETs

Farzan Jazaeri, Lucian Barbut, Jean-Michel Sallese

IEEE Transactions on Electron Devices > 2013 > 60 > 12 > 4034 - 4040

We have developed a closed-form solution for trans-capacitances in long-channel junctionless double-gate (JL DG) MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with technology computer-aided design simulations. According to this paper, a complete intrinsic capacitance network is obtained, which represents an essential step toward ac analysis of circuits...

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LOGIC GATES (13)
MOSFET (10)
SILICON (7)
FIELD EFFECT TRANSISTORS (6)
JUNCTIONLESS (6)
SEMICONDUCTOR DEVICE MODELING (6)
CAPACITANCE (5)
MOBILE COMMUNICATION (5)
VOLTAGE MEASUREMENT (5)
COMPACT MODEL (4)
DOPING (4)
ELECTRIC POTENTIAL (4)
JUNCTIONLESS (JL) (4)
NANOWIRE (4)
ANALYTICAL MODELS (3)
DOUBLE GATE (DG) (3)
NANOWIRES (3)
SEMICONDUCTOR PROCESS MODELING (3)
CAPACITORS (2)
ELECTRON TRAPS (2)
FERROELECTRIC (2)
INTERFACE TRAPS (2)
MATHEMATICAL MODEL (2)
NANOWIRE (NW) (2)
NANOWIRE. (2)
NOISE (2)
OFF-CURRENT (2)
OXIDE TRAPS (2)
SEMICONDUCTOR DEVICE MEASUREMENT (2)
VESFET (2)
28 NM BULK CMOS (1)
28-NM BULK MOSFETS (1)
4.2 K (1)
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AC ANALYSIS (1)
ACCUMULATION (1)
ADAPTATION MODELS (1)
ADVANCED CMOS (1)
AGING EFFECTS (1)
ANNEALING (1)
ASYMMETRIC (1)
BIOSENSOR (1)
BOOSTING (1)
CARRIER DENSITY (1)
CHARGE CARRIER DENSITY (1)
CHARGE TRAPPING (1)
CMOS (1)
CMOS TECHNOLOGY (1)
COMPUTATIONAL MODELING (1)
CONTROL SYSTEMS (1)
CRYOGENIC (1)
CRYOGENICS (1)
CURRENT MEASUREMENT (1)
CURRENT SENSING (1)
CURRENT SPLITTING (1)
DC (1)
DEGRADATION (1)
DESIGN SPACE (1)
DIBL (1)
DIFFUSION DOPING (1)
DOUBLE GATE (1)
DOUBLE GATE (DG) MOSFET (1)
DOUBLE GATE MOSFETS (1)
DOUBLE-GATE (DG) (1)
DOUBLE-GATE FET (1)
DOUBLE-GATE MOSFET (1)
DOUBLE-GATE NEGATIVE CAPACITANCE FET (DG NCFET) (1)
EKV (1)
EKV 2.6 (1)
ELECTRODES (1)
ELECTRON MOBILITY (1)
ELECTROSTATICS (1)
ENERGY STATES (1)
ENHANCEMENT MODE (1)
FABRICATION (1)
FERROELECTRIC MATERIALS (1)
FET (1)
FIELD EFFECT TRANSISTOR (FET) (1)
FINFET (1)
FOSS (1)
FREE CARRIER MOBILITY (1)
HALL EFFECT (1)
HIGH-<ITALIC XMLNS:ALI="HTTP://WWW.NISO.ORG/SCHEMAS/ALI/1.0/" XMLNS:MML="HTTP://WWW.W3.ORG/1998/MATH/MATHML" XMLNS:XLINK="HTTP://WWW.W3.ORG/1999/XLINK" XMLNS:XSI="HTTP://WWW.W3.ORG/2001/XMLSCHEMA-INSTANCE">K</ITALIC> (1)
HYSTERESIS (1)
HYSTERETIC (1)
INDUCED GATE NOISE (IGN) (1)
INTEGRATED CIRCUIT MODELING (1)
INTEGRATED CIRCUITS (1)
INVERSION (1)
JUNCTIONLESS (JL) FETS (1)
LOW VOLTAGE DEVICE (1)
LOW-POWER DEVICE (1)
MATCHING (1)
METALS (1)
MOBILITY (1)
MOBILITY EXTRACTION (1)
MOBILITY MEASUREMENT (1)
MODELING (1)
MOS DEVICES (1)
MOSFET CIRCUITS (1)
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INFONA - science communication portal

Search results for: Farzan Jazaeri

Charge-Based Modeling of Radiation Damage in Symmetric Double-Gate MOSFETs

Free Carrier Mobility Extraction in FETs

Characterization of GigaRad Total Ionizing Dose and Annealing Effects on 28-nm Bulk MOSFETs

Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation

Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing

Variability of Low Frequency Noise and mismatch in CORNER DOPED and standard CMOS technology

Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

Carrier Mobility Extraction Methodology in Junctionless and Inversion-Mode FETs

Modeling Channel Thermal Noise and Induced Gate Noise in Junctionless FETs

FOSS EKV 2.6 parameter extractor

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

Generalized Charge-Based Model of Double-Gate Junctionless FETs, Including Inversion

Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

Design space of twin gate junctionless vertical slit field effect transistors

Heavily doped junctionless vertical slit FETs with slit width Below 20 nm

A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

Trans-Capacitance Modeling in Junctionless Symmetric Double-Gate MOSFETs

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