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In Ultra-Thin Body and BOX Fully Depleted Silicon-On-Insulator (UTBB FD-SOI) technology, body biasing can be used to achieve better energy efficiency. We propose a simple Time, Energy, Power (TEP) model based on Ring Oscillators (RO) measurements to predict optimal (Vdd;Vbb) point for complex circuits and validate it against direct experimental measurements. The model predicted Adaptive Forward Body...
Seven FinFET devices optimized for 7nm technology along with three SRAM cells were evaluated and compared. The high_l device has the lowest OFF current and the highest ON/OFF current ratio. Moreover, 8T SRAM cell achieves the highest SNM which guarantees its robust operation. Hence, 8T SRAM cell using high_l devices is suggested as the choice of memory cell for the discussed 7nm FinFET process.
In this paper, we studied hole transport in highly scaled (down to 14nm-node) FDSOI devices, from 77K to 300K in the coupling condition. We studied mobility enhancement by Ge% and back biasing. Then, mobility degradation in short channel devices was intensively analysed and additional scattering mechanisms were revealed in terms of their origin and location.
Because of their many attractive attributes, FinFETs are emerging as the device of choice for CMOS process technology nodes below 20nm. This paper is the first work that investigates the effectiveness of building CMOS circuits operating in the near-threshold regime and above with 7nm FinFET technology through a cross-layer design and simulation framework. Three types of FinFET devices with different...
This paper discusses the influence of extensionless lengths (0nm-self aligned, 15nm and 20nm) on UTBB (Ultra-Thin-Body-and-Buried oxide) SOI (Silicon-On-Insulator) devices operating in conventional (VB=0V), Dynamic Threshold (DT2, where VB=VG) and enhanced Dynamic Threshold (eDT, where VB=kVG) modes. The extensionless device of 20nm (underlap between gate and source/drain) presents better SS (Subthreshold...
In his 1965 paper titled “cramming more components onto integrated circuits” [1], Gordon Moore predicted the number of components on a chip would increase exponentially with time due to continual reduction of feature sizes. That paradigm has continued successfully for the past 50 years, but cracks are starting to appear. Lithography is becoming prohibitively expensive and component quality is expected...
We describe a 3D integration process flow in which the vertical distance from the CMOS layer to the novel device layer is 100–1000 nm. This short distance effectively defines the process flow as a silicon CMOS process flow and allows for the use of silicon infrastructure in process and design. Progress has been made in demonstrating various pieces of III–V device integration into a foundry 0.18 µm...
A fast TSV identification algorithm is proposed in this work to reduce the test time of pre-bond TSV probing. The speeding up of the algorithm comes from two aspects. First, any unnecessary session during the test is skipped. Second, the test terminates as soon as either all TSVs have been identified or a pre-specified maximum number of faulty TSVs have been identified. Experimental results demonstrate...
This paper explores the effects of back-gate bias on switched-capacitor (SC) DC-DC converters in 28 nm UTBB FD-SOI. By using back-gate bias to optimize the control circuitry and switches, the SC converter can operate with a peak efficiency of 72% in sleep mode (100 nW load) and 83% in active mode (100 µW load).
Emerging connected devices operating on battery or harvested energy sources highlight the need for ultra-low standby power design. Including non-volatility in flip-flops (FF) allows nullifying the power consumption in sleep mode, while maintaining the system state. Most of the reported solutions require FF modifications while increasing their complexity. This paper presents a non-volatile flip-flop...
A novel concept of multi-body 1T-DRAM cell fully compatible with both planar Silicon-On- Insulator substrates and 3D architectures is presented. Its scalability is ensured thanks to the dedicated body partitioning for hole storage and electron current sensing, suppressing the super-coupling effect and allowing the coexistence of electron and hole layers in very thin silicon films. Numerical simulations...
A multi-threshold design methodology of stacked silicon nanowire MOSFETs is proposed. A flexible doping scheme is demonstrated for high-performance and low-operating power designs integrated together on a same substrate. With additional channel length adjustment, low standby power is further achieved.
The RF cryogenic performance of ultra-low-loss, wideband (DC to 40 GHz) single-pole double-throw (SPDT) RF switches implemented in a 180 nm SOI CMOS technology is reported for the first time. Results show that the switch insertion loss (IL), isolation (ISO), small- and large-signal linearity all improve as the temperature decreases. DC characterization of individual transistors was performed and analyzed...
In short-channel fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs, the drain leakage current is enhanced by the parasitic bipolar transistor. The parasitic bipolar effect is induced by band-to-band tunneling and floating-body effects. It strongly depends on film thickness and back-gate voltage. We show experimentally the possibility to reduce the parasitic bipolar effect by biasing the back...
This paper presents the characterization of inversion coefficient and technology current for 14nm FinFET. Analog performance parameters, their variability and controlability, including transconductance effieincy, intrinsic gain, gain-bandwidth product, flicker noise and current mismatching, are then characterized in terms of inversion coefficient. These characterized relations are used for sizing...
This work provides a detailed study of 28 nm fully-depleted silicon-on-insulator (FD SOI) ultra-thin body and buried oxide (BOX) (UTBB) MOSFETs for high frequency applications. RF figures of merit (FoM), i.e. the current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax), are presented for different transistor geometries. The parasitic gate and source/drain series resistances,...
In this work we propose and validate by experimentally calibrated simulations a silicon Tunnel FET(TFET) based capacitorless DRAM cell, implemented as a fully-depleted FinFET with CMOS compatible process. The devices have a conventional FinFET structure except for a p+ (for n-type TFET) doped pocket of length LPKT and doping NPKT between the intrinsic channel and the (n++) drain. This doped pocket...
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