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In Ultra-Thin Body and BOX Fully Depleted Silicon-On-Insulator (UTBB FD-SOI) technology, body biasing can be used to achieve better energy efficiency. We propose a simple Time, Energy, Power (TEP) model based on Ring Oscillators (RO) measurements to predict optimal (Vdd;Vbb) point for complex circuits and validate it against direct experimental measurements. The model predicted Adaptive Forward Body...
Seven FinFET devices optimized for 7nm technology along with three SRAM cells were evaluated and compared. The high_l device has the lowest OFF current and the highest ON/OFF current ratio. Moreover, 8T SRAM cell achieves the highest SNM which guarantees its robust operation. Hence, 8T SRAM cell using high_l devices is suggested as the choice of memory cell for the discussed 7nm FinFET process.
In this paper, we studied hole transport in highly scaled (down to 14nm-node) FDSOI devices, from 77K to 300K in the coupling condition. We studied mobility enhancement by Ge% and back biasing. Then, mobility degradation in short channel devices was intensively analysed and additional scattering mechanisms were revealed in terms of their origin and location.
Because of their many attractive attributes, FinFETs are emerging as the device of choice for CMOS process technology nodes below 20nm. This paper is the first work that investigates the effectiveness of building CMOS circuits operating in the near-threshold regime and above with 7nm FinFET technology through a cross-layer design and simulation framework. Three types of FinFET devices with different...
This paper explores the effects of back-gate bias on switched-capacitor (SC) DC-DC converters in 28 nm UTBB FD-SOI. By using back-gate bias to optimize the control circuitry and switches, the SC converter can operate with a peak efficiency of 72% in sleep mode (100 nW load) and 83% in active mode (100 µW load).
Emerging connected devices operating on battery or harvested energy sources highlight the need for ultra-low standby power design. Including non-volatility in flip-flops (FF) allows nullifying the power consumption in sleep mode, while maintaining the system state. Most of the reported solutions require FF modifications while increasing their complexity. This paper presents a non-volatile flip-flop...
A novel concept of multi-body 1T-DRAM cell fully compatible with both planar Silicon-On- Insulator substrates and 3D architectures is presented. Its scalability is ensured thanks to the dedicated body partitioning for hole storage and electron current sensing, suppressing the super-coupling effect and allowing the coexistence of electron and hole layers in very thin silicon films. Numerical simulations...
The RF cryogenic performance of ultra-low-loss, wideband (DC to 40 GHz) single-pole double-throw (SPDT) RF switches implemented in a 180 nm SOI CMOS technology is reported for the first time. Results show that the switch insertion loss (IL), isolation (ISO), small- and large-signal linearity all improve as the temperature decreases. DC characterization of individual transistors was performed and analyzed...
In short-channel fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs, the drain leakage current is enhanced by the parasitic bipolar transistor. The parasitic bipolar effect is induced by band-to-band tunneling and floating-body effects. It strongly depends on film thickness and back-gate voltage. We show experimentally the possibility to reduce the parasitic bipolar effect by biasing the back...
In this work we propose and validate by experimentally calibrated simulations a silicon Tunnel FET(TFET) based capacitorless DRAM cell, implemented as a fully-depleted FinFET with CMOS compatible process. The devices have a conventional FinFET structure except for a p+ (for n-type TFET) doped pocket of length LPKT and doping NPKT between the intrinsic channel and the (n++) drain. This doped pocket...
This paper presents our recent development of an ASIC for automotive application. With the progress of automotive electronics, there is increasing need for high temperature and high voltage operation. The ASIC for the EPS applications was integrated with a boost gate driver, three-phase inverter drivers and their components. The ASIC was designed and fabricated using SOI-BiCD process which can operate...
This paper presents an ultra-low power receiver design at 920MHz. We proposed a receiver architecture, in which bias switch technique is applied to reduce power consumption significantly. The receiver was simulated and laid out on 65nm SOTB CMOS technology, consuming only 53uW at 0.6V supply voltage. It achieves a sensitivity of −82dBm with a data rate of 10 – 100 kbps.
This paper proposed an on-chip low power Body Bias Generator (VBBGEN) for ultra low leakage at 65nm SOTB (Silicon on Thin Buried Oxide) logic circuits at sleep mode. In the results of post layout simulation, the VBBGEN can generate and apply up to −2V body bias at a supply voltage of 0.5V with a current consumption of less than 361nA. By using the VBBGEN, it is expected that sleep current of CPU on...
Recent technological advances in monolithic 3D integration lay the foundation for highly efficient next-generation computing systems. These advances, however, can only be utilized to their full potential if system architectures are properly optimized by utilizing monolithic 3D-IC technology for target applications. Thus, a multidisciplinary research framework from system architecture to technology...
In this paper, we analyze the variability of III–V homojunction tunnel FET (TFET) and FinFET devices and logic circuits operating in near-threshold region. The impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, two-way NAND delay, switching energy and leakage power are investigated and compared using 3D atomistic TCAD mixed-mode...
This work investigates the impact of Random Telegraph Signal (RTS) noise on a 6-Transistor Single-P-Well Static Random Access Memory (6T-SRAM) in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB FD-SOI) technology. RTS noise impact is observed through Write-Ability measurements on a 143Kb SRAM macro. A SPICE-level bias- and time-dependent RTS model peculiar to UTBB FD-SOI,...
This paper studies the potential of Si-Ge TFET for low-power embedded memory blocks in reconfigurable platforms. The key observations from the comparative analysis of FinFET and TFET based EMB are summarized in Fig. 14. At low frequency, switching to the TFET cell from FinFET provides lower read power but degrades read stability, which can be improved through circuit techniques (TFETB). However, as...
Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate...
We demonstrate a flexible version of the semiconductor industry's most advanced transistor topology - FinFET on silicon-on-insulator (SOI) with sub-20 nm fins and high-κ/metal gate stacks. This is the most advanced flexible (0.5 mm bending radius) transistor on SOI ever demonstrated for exciting opportunities in high performance flexible electronics with stylish product design. For the first time,...
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