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In this paper, an integrated noise source realized with silicon Schottky diodes is presented. To this aim, dedicated test structures have been designed and characterized; the corresponding Schottky diodes feature an avalanche breakdown voltage close to −6 V. When biased around this breakdown voltage (their anode is grounded), an adjustable Excess Noise Ratio, ranging between 4 dB to 20 dB, was achieved...
We developed VTSTs for 6T-SRAM and RL-SRAM and evaluated them to investigate the influences of SRAM operation by Vth fluctuation using measured FCMs and CΔVths. As a result, we successfully confirmed the superior immunity of Vth fluctuation of the RL-SRAM than the 6T-SRAM.
This paper presents the design of a Broadband CMOS RF Power Amplifier, suitable to be stressed at circuit level but with the possibility to be measured both at circuit and at device level. It allows establishing a relation between the degradation of circuit's RF performances and those of its individual devices parameters. The test structure, measurement set-up and procedure are described in detail.
Due to their flexibility and compatibility with silicon devices, the use of carbon nanotubes as scaffolds for metal interconnect in flexible and wearable electronics has been proposed. This paper examines the performance of dual-height carbon nanotubes as flexible scaffolds for horizontal and vertical interconnects. For this purpose, a number of test structures have been designed and fabricated and...
A 6-pad True Kelvin Test Structure for advanced CMOS devices is proposed in this work. It allows test engineers to make very accurate and repeatable wafer-level measurements required for SPICE modelling applications. This design helps to overcome parasitic resistance of the probe holder and probe which is found to be dependent on test temperatures. It also mitigates increase in probe contact resistance...
In this paper we present a new test vehicle designed for Resistive Random Access Memories (RRAM) arrays (from single bit to 1Mbits) characterization. The arrays structure, the decoders, and the selectors are explained as well as the electrical setup that drives the array decoders and performs the electrical characterization. Eventually, we discuss some electrical results concerning the switching voltage...
This paper presents a new methodology to characterize the GaN buffer doping level which is a critical parameter for epitaxial fabrication of GaN wafers. As demonstrated in this study, its characterization is challenging due to parasitic effects. Capacitance-Voltage (C-V) measurements are carried out on a Metal Insulator Semiconductor (MIS) structure with a gate on Al2O3 dielectric using a novel configuration...
This paper presents a test setup to characterize current collapse effects in power diodes such as GaN-based Schottky junctions. The setup principle and its main parts are described. Current/voltage transients can be recorded very shortly (2 microseconds on wafer prober) after reverse to forward switching. The related trapping effects are analyzed through temperature dependent measurements.
Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is an important concern for many analog CMOS integrated circuits. In this paper, transistors with enclosed gate layout are examined and compared with standard layout transistors, with particular emphasis on weak inversion region. Enclosed gate transistors show an improved gate voltage mismatch in weak inversion. A compact MOSFET...
Mismatch factor of SRAM bit cell and noise factor that affects its power up state are measured using 256 bit SRAM PUF test structure with bias voltage inputs. Probability of power up state is used to extract a mismatch factor normalized by σn (sigma noise voltage). By combining shifted bias voltages and repeat evaluation, whole 256 bit mismatch factors from real SRAM with small modification are obtained...
Greek crosses and TLM test structures were fabricated and characterized along with top-gate field effect transistors. We also show the usefulness and adaptation of a single TLM structure into multiple bottom-gate FETs that allow for extraction of contact resistance and typical device parameters for direct correlation on the same TMD flake enabling very little variability that can occur “flake to flake”...
Thanks to an innovative design, stress-strain curves of released thin films can be obtained, from zero stress up to the tensile fracture stress of the material, using internal stress present in a second material. This second material acts as an actuator that pulls on the sample when released from the substrate, allowing to apply a stress on the tested material. This technique has also been used to...
We propose an arrayed test structure to assess the damages of metal-oxide-semiconductor field-effect transistors (MOSFETs) exposed under back-side LSI processes, such as by Focused Ion Beam (FIB). Back-side process with FIB is becoming essential to analyze and repair modern LSI chips, to avoid processing through many metal layers with dense wiring and dummy patterns. To access transistors from back-side,...
In this work, an upgraded version of the so called New Y function [1] MOSFET parameter extraction methodology is proposed, taking the impact of access resistance into account. This new approach emphasizes the importance of considering access resistance variation with gate bias when extracting MOSFET parameters.
It is not so easy to correlate DC Kelvin measurement data of an RF transistor and its non-Kelvin RF measurement data, because the actual bias voltages in the latter are not known precisely. Knowing the bias voltages requires accurate characterization of its embedding structure. This paper reports on an attempt at correlating DC and RF measurements of parasitic resistances associated with a MOSFET...
Test structures were produced for optimizing the design and fabrication of a patterned solid polymer electrolyte in an electrochemical oxygen sensor. Measurements showed that choice of photoresist developer and the underlying insulator material affected durability of the polymer structures. Test electrodes covered by the polymer were effective at supporting electrochemical oxygen detection.
A detailed statistical characterization of the drain current low-frequency noise (LFN) in sub-15 nm Si/SiGe Trigate NW pMOSFETs is presented. The slow oxide trap density and distribution, as well as the correlated mobility fluctuations effect are probed for several channel geometries. The LFN variability scaling is also presented and compared to established nano-scale planar CMOS technologies. Our...
Developing MEMS sensors with a high strain sensing range (up to 0.6) and a stepwise sensing mechanism could enable widespread downstream applications, by allowing intimate, mechanically conformable integration with soft biological tissues. Most approaches to date focus on challenges to associate the sensing mechanism with high peak strains under large deformation. By designing and characterizing test...
We apply the contact-end resistance method to TLM structures in order to characterize the graphene-metal contact resistance. A critical analysis of the experimental results shows that the commonly used transmission line model fails to accurately describe the graphene-metal contact under specific biasing conditions. The experiments suggest the presence of an additional resistance contribution associated...
The energy band diagram is a primary feature of any semiconductor device and determines its physical parameters and practical applicability. The most effective technique of band diagram characterization is the photoelectric measurement based on internal photoemission phenomena in the layered structures. In the technologically important metal-insulator-semiconductor (MIS) structures, the most important...
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