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2.1D package technology (chip on substrate) as a potential low cost solution for 2.5D silicon interposer package (chip on wafer on substrate), we develop here a panel type manufacture organic interposer (scheme 1). 2.1D technology focus on the production cost and the ball count range which defined by line/space. We presents the demonstration of high resolution photolithography semi-additive processes...
The fabrication of passive RF structures in the millimeter wave frequency range with conventional printed circuit technology is subjected to some disadvantages (available design rules, dimensional accuracy and tolerances) compared to ceramic circuit carriers. The here presented SPE (sequential pre etching) process technology allows a significant reduction of these disadvantages, without diminishing...
Via last TSV (through silicon via) technology is more and more applied in 3D WLCSP, which can decrease package volume and increase I/O density. The process of via last includes temporary bonding, grinding, photolithograph, silicon etching, SiO2 etching, CVD, PVD, plating and so on. Silicon etching and SiO2 etching are important process of via last TSV package for interconnect technology. Temporary...
Ultrasonic cleaner is a workhorse in all failure analysis labs for residue removal after decapsulation or etching. In this paper, we present a novel method of ultrasonic decapsulation, where acid mixture was used in conjunction with ultrasonic agitation and was discovered to provide exceptionally high quality preservation of the surface of the copper bond wires which exceeds the quality of laser decap...
Wafer level package (WLP) sample is one of the most popular packaged methods due to its low cost (wafer batch process), high performance, small form factor and low assembly cost [1]. Decapsulation is necessary for failure analysis. Fig. 1 and Fig. 2 are the sketch maps of the WLP wafer with Sn balls on the chip. The stannum (Sn) ball on the package need be removed while the copper line (Re-distribution...
The RC delay, electro migration (EM) and TDDB performance become more challenges to meet device requirement as continuous geometry shrink on BEOL dual damascene interconnects. To overcome these challenges from interconnect patterning point of view, we proposed Cu subtractive RIE as a potential solution for next generation Cu/Low-k interconnects.
This work addresses the design and the fabrication of small scale square planar coils with high density of turns and self inductances up to 170 μH. First, the modified Wheelers formula is used to determine the optimal number of turns in order to achieve the highest inductance. Then, an effective process flow based on polyimide (PI) and copper processing is presented, and the key aspects of the processing...
This paper presents a die-level post-CMOS processing protocol for multi-layer homogeneous 3D integration with adhesive bonding technique using parylene-C as an intermediate bonding layer and sidewall passivation material. This protocol was used to fabricate 4-layer CMOS memory chip stacks, which were then packaged and tested using time domain reflectometry (TDR) measurement technique. The results...
We report the fabrication of graphene quantum dots on Cu substrates by thermal CVD. The synthesized high-density graphene quantum dots exhibit strong surface enhanced Raman scattering (SERS) effects. The nanoscale distance of 30∼50nm between neighboring quantum dots combined with quantum dots to form nanostructures favorable for plasmonic coupling enhanced high local electric fields, which lead to...
In this paper, the interface adhesion and reliability between copper lead frame(C-19210) and resin prepreg material of different copper lead frame lamination pretreatment processes (CZ and brown oxide) was studied. Surface morphology, roughness, peel strength and moisture sensitivity level, MSL3, reliability tests were performed in order to investigate the performance between these pretreatment procedures...
Pulsed capacitively coupled plasmas (CCP) was applied to self-aligned-via (SAV) based all-in-one (AIO) etching process. Effects of bias and synchronous pulsed plasmas on the AIO etching process were analyzed to improve the reliability and reduce the RC delay in back-end-of-line (BEOL) copper interconnect system. For steps of hard-mask open and partial via etch, synchronous pulsed plasmas were applied...
In this paper, wet cleaning solution compatible with cobalt are investigated to achieve low Co etching rate on blankets film and no film attack on patterned 14nm wafer after line and via etching. Proposed solutions are compared to conventional wet cleaning solutions [5],[6].
With the trend towards miniaturization IC-manufacturers are permanently requested to increase the density of interconnects generating conductors featuring finer lines and spaces. Advanced manufacturing technologies such as Semi-Additive-Processing (SAP) and advanced Modified-Semi-Additive-Processing (aMSAP) were devised, realized and implemented in order to meet the requirements.i According to the...
In recent years, high-end interconnects have enabled signal transmission rates of tens of gigabits per second (Gbps) in printed circuit boards (PCB). Reducing the transmission losses induced by conductor surface roughness in a PCB is important from the standpoint of signal integrity. In this study, we measured the effects of surface roughness in a PCB using a dielectric rod resonator method. Then,...
“Saturation Etching” is the method we have developed for decapsulating silver wire packages using a chemical solution. This method is also effective for copper wire packages, and damages to wires can be minimized by dissolving copper into acid.
Trench-first-metal-hard-mask (TFMHM) approach has been widely utilized for copper interconnect formation since 45nm CMOS technology node [1–3]. Trench patterns are defined by MHM etch. These trench patterns not only control final Cu line shape and location, but also will affect the subsequent via patterning because via pattern is self-aligned (at least partially) to trench pattern [4,5]. With continuously...
In this paper, a lead frame package with trace routing capability is proposed for advanced QFN package that has copper traces to connect with pads or dies, called routable aQFN package. Four packages were conducted to evaluate the trace routing capability. The first is wire bond type 11 mm ×11 mm 141 I/Os package with trace fan-out designs. The second is wire bond type 3.2 mm × 3.2 mm 48 I/Os package...
In recent years, the data center reliability is paid more attention due to in cloud computing application. In general, the longer term reliability requirement is concerned for it than in general products when in service life. With the more and more severe environmental pollution, the air quality will also directly or indirectly influence the life of data center wherever indoor and outdoor. The air...
IC package substrates are normally fabricated by semi-additive process (SAP) for high-density packaging. Dow's brand new Ni-free electroless copper chemistry developed for SAP offers new solutions for the future fine pattern design to IC substrate production. The new developed chemistry shows high productivity (0.6um/20min) and peel strength (over 0.5kN/m on 100nm roughness) and improved micro via...
With the miniaturization, multifunction, high speed development of the chip and package, the requirements for package substrate and 3D packaging becomes higher. As the IC line size continues to decrease, the signal transmission rate continues to improve and the amount and density of pin is getting more and more, the Pad pitch of package substrate which connects to it must be smaller and smaller. The...
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