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Chaotic systems can be used for secure communication such as transmitting video, audio and text files. Various chaotic generators have been implemented on FPGA in realtime for synchronous communication applications. In this paper, a detailed design approach is presented to implement modelbased chaotic generator designs on FPGA. Henon map has its significance in studying chaotic systems and is used...
In the past decade, the number of reported security attacks exploiting unchecked input firmware values has been on the rise. To address this concerning trend, this work proposes a novel detection framework, called DOVE, capable of identifying unlikely firmware execution flows, specifically those that may reveal a security vulnerability. The DOVE framework operates by leveraging a symbolic simulation...
Chip level Functional verification of processor based IC designs predominantly use directed test cases implemented in high level programming languages like "C". The verification test case software (SW) runs on the control core of the IC and configures different IPs to implement a particular functionality that verifies a set of functional requirements. Chip level verification environment...
A Self-rePAiring spiking Neural NEtwoRk (SPANNER) hardware architecture is presented in this paper. It is based on a software model of an astrocyte-neuron network which previously demonstrated the ability to self-detect faults and self-repair autonomously. Experimental results in this paper show that when faults occur at the synapse, remaining healthy synapses of the same neuron are enhanced by the...
Architecture of fast data recovery was introduced into the design of the digital receiver in UHF RFID Reader. The data should be recovered in a short time for the next step of decoding. Rich synchronizing information in Miller coding was used to improve the quality of decoding in a poor situation. The architecture of fast data recovery consisted of edge detector, period measure, cnt_syn and data recovery...
Traditional hardware description languages are limited when describing highly configurable and reusable hardware components. The paper introduces methodology based on a Python language for design of hardware component generators on higher abstraction level. The scripting language is used to produce customizable cycle accurate hardware behavior and open-source tools provide automatic conversion to...
In the paper the implementation on reconfigurable hardware of a Sugeno type neuro adaptive fuzzy inference system is proposed to be presented. The pipeline and parallel pipeline architecture play an important role in modelling the algorithm for the FPGA based implementation. In order to design the pipeline-parallel model of the controller two different methods were used: high level synthesis tool...
In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of...
Time-predictability is an essential property of software components of safety-critical hard real-time systems. Single-path code generation produces code that forces every execution to follow the same trace of instructions, thus making the execution time of code independent of its input data. This supports the time predictability of components and simplifies their worst-case execution-time analysis...
In this paper, a new linear feedback shift register (LFSR) structure for scan-based built-in self-test (BIST), which has at least two characteristic polynomials, is proposed. Multiple polynomials are utilized to generate the pattern sequences for feeding the scan chain of the circuit under test in pseudorandom testing phase. Using the proposed LFSR, same or even better fault coverage can be achieved...
Matlab/Simulink is today's de-facto standard for model-based design in domains such as control engineering and signal processing. Particular strengths of Simulink are rapid design and algorithm exploration. Moreover, commercial tools are available to generate embedded C or HDL code directly from a Simulink model. On the other hand, Simulink models are purely functional models and, hence, designers...
A a system on-chip architecture performing the task of moving object detection and labeling in video data is proposed in the paper. The solution involves task partitioning between the microprocessor-bound software and the dedicated hardware coprocessor. A detailed description of the system is given, along with the analysis of the hardware/software decomposition process. A summary of the resources...
Post-Silicon Validation faces numerous challenges in the areas of test generation efficiency, time utilization and comprehensive coverage of the various functionalities of advanced microprocessors. The proposed approach uses the concept of building a Master Test Program that is used to build multiple test-streams by utilizing an instruction pool and a data pool. It utilizes lightweight modules such...
ASIP are needed to handle the future demand of flexible yet high performance computation in mobile devices. However designing an ASIP is complicated by the fact that not only the processor, but also tools such as assemblers, simulators, and compilers have to be designed. No GAP is a design automation tool for ASIP design that imposes very few limitations on the designer. Yet No GAP supports the designer...
Early architectural exploration and design validation are becoming increasingly important for multi-processor systems-on-chip (MPSoC) designs. Native functional simulations can provide orders of magnitude in speedup over cycle or instruction level simulations but often require dedicated maintenance. In this work, we present a tool called NATIVESIM to automatically generate the functional models for...
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. By embedding Chisel in the Scala programming language, we raise the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and...
For mobile user equipments (UE) a careful power management is essential. Despite this fact, quite an amount of energy is wasted in todays UEs analog and digital frontends. Those are engineered for extracting the wanted signal from a spectral environment defined in the corresponding communication standards with their extremely tough requirements. In a real receiving process those requirements can typically...
Traditionally, common processor augmentation solutions have involved the addition of coprocessors or the datapath integration of custom instructions within extensible processors as Instruction Set Extensions (ISE). Rarely is the hybrid option of using both techniques explored. Much research already exists concerning the identification and selection of custom hardware blocks from hardware/software...
This paper presents the implementation of the error recovery scheme from temporary faults, applicable for datapaths of coarse-grained reconfigurable architectures. We have chosen the DART architecture as a vehicle to study various aspects related to implementation of the instruction retry in a complex highly parallel reconfigurable system. Synthesis results have confirmed the time, hardware, and power...
The most significant source of lost performance when a thread migrates between cores is the loss of cache state. A significant boost in post-migration performance is possible if the cache working set can be moved, proactively, with the thread. This work accelerates thread startup performance after migration by predicting and prefetching the working set of the application into the new cache. It shows...
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