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Circular-polarized (CP) radiation is found to be a viable choice for imaging/sensing applications by offering faster scan time and robust source-detector alignment compared to linear radiation [1]. Power-efficient generation of a low-noise, high-power mm-wave/THz circular-polarized signal in silicon continues to be a challenging task. Due to limited output power of transistors at mm-wave, power combining...
This paper presents an ultra-broadband low-noise amplifier (LNA) operating from 16 to 43 GHz in a 0.25 pm SiGe:C BiCMOS technology. Across this band, the LNA achieves simultaneous low-noise performance (2.5–4.0 dB) and power matching (S11 < −10 dB) using dual-LC tank matching. The measured minimal noise figure is 2.5 dB at 26 GHz with an average value of 3.25 (±0.75) dB from 16 to 44 GHz. The best...
In this paper, a simple and fast de-embedding procedure suitable for the X-parameter measurement is presented. The X-parameters of the dummy structures including open and short are measured and then directly subtracted from the device under test (DUT) to remove parasitic effects. Compared with the conventional procedure, this approach can provide a fast and simple algorithm based on the matrix transformation...
This paper presents a 1.3mA current stimulator integrated circuit (IC) with closed-loop, active charge balancing for nerve interfacing applications. The stimulator employs two current-based digital-to-analog converters (DACs), one each for anodic and cathodic phases, with binary-weighted transistors and 2b-programmable least-significant bit (LSB) currents. The biphasic, cathodic-leading, stimulus...
This paper proposes a new architecture of 12-bit current-steering digital-to-analog converter (DAC) with novel biasing scheme. In the proposed DAC, two 6-bit binary-weighted current source arrays are designed with two reference currents. The technique allows significant area savings without impairing static accuracy. The paper also presents a method to generate dual reference currents, whose design...
In this paper we investigate the effect of a discontinuity, at the measurement reference plane, on loadpull measurements of high-power RF transistors. The discontinuity is created by transition from the microstrip transformers on the printed-circuit board of the test-fixture to the packaged transistor. Our measurements indicate that the discontinuity does not change the peak performance of a packaged...
A power amplifier for a frequency range of 11–13 GHz that is incorporated in 0.35 SiGe-technology is presented in this letter. The two-stage push-pull amplifier uses monolithically integrated transformers for input and interstage matching and a monolithically integrated modified LC-balun as an output—matching network. For stabilization purposes and gain improvement in the operating frequency...
This article is concerned with the suggestion and the practical realisation of the power amplifier (PA) with the modern LDMOS transistor (BLF368) for the non-standard RF band 144 MHz. This amplifier is very linear and works in the AB class with the opening angle about 100°.
A negative impedance is used to enable distortion cancellation between the transconductor and the cascode transistor for LNAs with a cascode topology. As a proof of concept, a resistive feedback LNA using this IM3 cancellation technique in a standard 0.16µm CMOS process shows that for 0.1GHz to 1GHz, improvements of 6.3dB to 10dB for IIP3 and 0.2dB to 1dB for gain are achieved without noise degradation...
A new technique is proposed for the design of linear and power amplifiers at mm-wave frequencies where load-pull of large transistor output cells is difficult. The technique transforms the load-pull data on a small, standard foundry transistor layout to a pair of common-gate contours for the intrinsic device; one gate-source and one gate-drain. These are then recombined as an intrinsic drain-source...
A low-power digitally-controlled variable gain low noise amplifier is implemented in a 40-GHz fT 0.25 ??m BiCMOS process. Wideband input matching independent of the variable gain, as well as high reverse isolation are achieved thanks to a partial feedback technique. The variable gain is based on a resistor-chain gain-control technique, leading to fine gain steps and constant output impedance. It covers...
This paper presents a fully integrated V-band two stage power amplifier with cascode topology. The PA is designed on 0.25 ??m SiGe:C BiCMOS technology. The technology provides ft and fmax ?? 200 GHz. The two stage PA provides a gain of 17 dB at 64 GHz. The PA has been optimized for biasing circuit, PA Core and the matching networks. This has resulted in high power and high linearity from 58 GHz to...
In this paper, for the first time, silicon integrated tuner is presented aiming silicon transistor (HBT, MOSFET) millimeter wave (MMW) noise parameters (NFmin, Rn, Gammaopt) extraction through multi-impedance method. This tuner is directly integrated in on-wafer tested transistor test structure. Design, electrical simulation and MMW measurement of the Tuner are described showing capability from 60...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
A 53 dB gain limiting amplifier for OC-192 and 10 GbE applications is developed in a 50 GHz fT SiGe SOI complimentary bipolar process, and has 5 mV pk-pk sensitivity, 1.25 V pk-pk maximum input signal, 14 ps (20/80%) rise/fall times and 450 mV pk-pk output into matched differential 50 Ohm loads, consuming 430 mW on a 3.3 V supply. Input Cherry-Hooper gain stages limit the -3 dB bandwidth to 11 GHz...
A monolithic bipolar current follower has been developed, which can be used in conjunction with commercially available voltage followers to realize numerous linear electronic functions.
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