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An incremental delta-sigma modulator with a self-making capacitor having a high voltage operating ability for a 12-cell battery pack is proposed in this paper. The measured voltage range for each battery is from 0 to 5 V, and the maximum input voltage reaches to 60 V. The self-making capacitor adopting a metal over poly silicon with a relatively thin layer of oxide between the two plates is generated...
This work proposes a new gate driver circuit which utilizes hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) for high-resolution panels. By using one TFT to separate the output node from the capacitor in the gate driver circuit, the driving TFT can remain high speed to pull down the output signal. Simulation results verify that the falling time reduces over 20% without enlarging...
An incremental ADC (lADC) using parallel counting is proposed to achieve both high accuracy and power efficiency. By operating the IADC and the counting logic alternatively within two clock phases, the proposed scheme finishes a full conversion within fewer conversion cycles. The only additional circuitry for the parallel counting is a single comparator, much less than the add-ons in other multi-step...
This paper presents a biopotential acquisition unit with an instrumentation amplifier and analog-to-information converter for wearable health monitoring applications. The instrumentation amplifier defines the quality of the acquired biopotential signals. At the heart of the system is an Analog to Information Converter (AIC) to enables the random under-sampling operation. AIC is used to digitize the...
This paper presents a low-power on-chip RC oscillator with compensation for temperature and supply voltage variation. This circuit is based on a conventional on-chip oscillator, with only a capacitor and a comparator to avoid mismatch. Multiple current sources flow through the same resistor to generate a reference voltage. This is complemented with the dynamic element matching technique to reduce...
This paper proposes a pipelined time stretching technique for high throughput counter-based time-to-digital converters (TDC). Time stretching technique is used to increase the resolution of counter-based TDCs, yet it carries an inherent weakness of having a long conversion time due to the stretching phase. Without significant increment of chip area, the proposed pipelined time stretching method is...
Digital discrete-time implementations of non-Foster circuit elements offer an alternative approach to the design of devices such as negative capacitors and negative inductors. However, practical implementations of high-speed digital non-Foster circuits are affected by latency and noise, where latency can arise from analog-to-digital conversion time and computation time. Thus, the present work explores...
This paper presents a comparable study of the locking characteristics of phase-locked loops (PLLs) with an integrating bang-bang phase detector with that of PLLs with an Alexander full-rate bang-bang phase detector. Both periodic and single-event data transients are used to investigate the lock performance of two PLLs with identical configuration and components but different phase detectors. Simulation...
This paper presents a discrete time fully differential CMOS signal conditioning circuit for acquisition of biosignals. It is realized using switched capacitors (SC), which provides reconfigurability, high precision, high CMRR and low sensitivity to temperature and process variations. However, the SC circuit suffers from various errors like charge injection and clock feedthrough which have an impact...
This paper presents the design and simulation of a two stage power management circuit implemented in 0:18μm CMOS that operates from very low voltages starting from 460mV and higher up to a maximum of 800mV. The proposed capacitive power management unit consumes very low power of 11μW @ 500mV sufficient to be operated from tiny photovoltaic cells, dimensions of few mm2. In addition to the lower power...
In this paper, a 6-bit 320-MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented. The 2-bit/cycle technique and tri-level based charge redistribution technique are utilized to achieve high conversion rate and reduce the hardware cost. The proposed ADC is designed and implemented in a 65-nm CMOS process. Simulation results show that it accomplishes 48.52-dB SFDR,...
There is renewed interest in the use of non-Foster circuit elements in a variety of important applications such as wideband impedance matching and artificial magnetic conductors. Although non-Foster devices such as negative capacitors and negative inductors can be realized using current conveyors and Linvill circuits, a digital design approach may offer an important alternative in some applications...
The current work proposes a low emission frequency shift keying (FSK) non-PLL based modulator for transmitting neural signals. FSK has been shown to be viable alternative to widely used ASK (Amplitude Shift Keying). Designers need to start developing low Electromagnetic Interference (EMI) algorithms for implanted devices so as to minimize interference. The proposed algorithm utilizes a ramp to modulate...
Continuous-time auto-zero and ping-pong operational amplifiers dedicated to space applications are proposed. The circuits were implemented in a standard 130 nm CMOS technology. They have been irradiated to evaluate their low-dose-rate radiation sensitivity. Measurement results show that these architectures can provide an input offset voltage lower than 1 µV. Comparisons with commercial low offset...
This paper presents the comparison between multistage amplifier and folded cascode amplifier design using 0.18μm CMOS technology. The objective of this project is to compare gain and power dissipation between these two design models. Sample and hold circuit (SHC) is the main component in pipelined ADC. Designing a low power, high gain SHC is crucial, that is the main reason why multistage amplifier...
A design of opamp-sharing multiplying digital-to-analog converter (MDAC) used in the successive stages of an 80MS/s 14-bit pipelined analog-to-digital converter (ADC) with 1.8V supply voltage is presented in this paper. Opamp-sharing structure of the paper is proposed to achieve low-power operation, and SC-CMFB (switch capacitor-common mode feedback) circuit further reduces power consumption. The...
A low power smart temperature sensor followed by an SC amplifier, buffer stage and a 12bit Successive-Approximation analogue-digital converter (ADC) for autonomous multi-sensor systems is presented. The proposed design is accurate within 0.1°C over the temperature range of −55°C to 125°C. A PTAT source like the one presented in [1] was used as a high accuracy temperature sensor. The read-out enables...
A 4-phase cross-coupled charge pump with charge sharing clock scheme is proposed in this paper. Four phase clock is utilized to prevent the reverse leakage current. A charge sharing clock control circuit is constructed, and the consumption in charging or discharging the bottom plate parasitic capacitance of the boost capacitors is reduced by half. The proposed charge pump is overstress free and compatible...
A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional...
This paper proposes the design of a binary search ADC that uses two different techniques, namely, distributed-residue and folding. These can prevent signal dependent offset and reduce the switching network complexity. A 5-bit binary-search ADC applying such proposed techniques has been developed in 65 nm CMOS. It consumes 540 μW under 1V supply voltage at the operating frequency of 600 MS/s. The simulation...
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