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This paper reviews Network-on-Chip architectures with prioritization of selected data streams targeting runtime reconfigurable manycore systems. The common idea of these architectures is to minimize the latency of selected packet transmissions by either bypassing or parallelizing processing stages in routers or by using dedicated links bypassing complete routers. Potential classes of selected data...
This paper proposes the design of a 10-bit Segmented-Hybrid Digital Pulse Width Modulator (DPWM) featuring a counter with segmented delay lines and an tunable digital Proportional-Integral-Derivative (PID) controller for digital DC-DC converters using AMS 0.35μm CMOS process. On the basis of simulations, the proposed DPWM dissipates ~55% lower power than the Hybrid DPWM with small area overhead (~8%)...
In this paper, a Johnson-encoded Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. The proposed FIFO which can be used to interface modules in Voltage/Frequency Islands (VFI) based Networks-on-chip, is capable of alleviating the excessive energy consumption and high performance overhead of the conventional...
This paper is to explain about the picture in picture technology that is used innovatively for automated wireless home security. The present home security system needs an LCD screen that is located somewhere inside the home to view the camera video. At some point of time, consider the time when you are watching a very interesting program in the television, may be the last over of a T-20 match or the...
This paper presents a method to match the clock frequency in multi-rate systems by extracting the SYNC clock. This method is applicable to all multi-rate hierarchical master-slave systems and synchronous digital hierarchy (SDH) networks in which master and slave are designed to work at different clock frequencies. Using the presented method, any system can be added to the network whose clock frequency...
Reducing leakage dissipation is becoming more and more important in low-power design. The dynamic energy dissipation reduction of adiabatic circuits using power-gating schemes has been introduced. In order to reduce leakage losses of the adiabatic circuits using power-gating schemes under deep submicron process, this paper proposes a MTCMOS (Multi-Threshold CMOS) power-gating scheme for adiabatic...
This paper simulates a current mode controlled separately excited dc motor in continuous conduction mode as well as in discontinuous conduction mode. The bifurcation phenomena have been explored with input voltage and speed error amplifier gain as bifurcation parameter. The study is helpful in selecting the range and combination of parameters if the mode of operation of the motor needs to be restricted...
This paper reviews an analog multiplier and divider using only single multiple-output current controlled current through transconductance amplifier (MO-CCCTTA). The proposed circuit can function as a four-quadrant multiplier and two quadrant divider without changing original circuit topology. A constant value of multiplication and division can be controlled via an input bias current and temperature-insensitive...
This paper presents an analog to digital converter (ADC) capable of resolving 8 bits at a sampling rate of 250 MSPS. Primary objective of the design has been to make a trade-off between power consumption and resolution while keeping the sampling rate high. The parallel-pipeline architecture was best fit for such requirements. A new sub-ADC scheme has been introduced here to remove possible switch...
The design and implementation details of a 4-bit time interleaved successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Low latency SAR ADC has been implemented by detecting two bits per clock cycle. Major contribution of this paper is that it uses only two capacitive DACs instead of three capacitive DACs. This is achieved by using...
Settling time is a crucial design issue in Phase-Locked Loop (PLL) used in modern wireless communication systems. A Digitally Controlled Oscillator (DCO)-based multi-operational modes All-Digital PLL (ADPLL), which can achieve an ultra fast settling time of 10 ??s, has been intensively researched. This paper describes a novel Counter-Based Mode Switching Controller (CB-MSC) for the ADPLL to further...
In this paper, a method of testing a flash A/D converter is presented. The flash A/D is first reconfigured as a propagation type A/D and it is tested afterwards. It is shown that the testing method is suitable for a fully automated use i.e. without the need of external devices.
Magnetic quantum dot cellular automata (MQCA) have been recently proposed as an attractive implementation of QCA as a possible CMOS technology substitute. Marking a difference with respect to previous contributions, in this work we show that it is possible to develop and describe complex MQCA computational blocks strongly linking technology and having in mind a feasible realization. Thus, we propose...
This work presents a periodic arbitrary waveform generator based on a ring oscillator structure implemented in a 0.13 mum SiGe BiCMOS technology. Using 16 delay stages with control programmable weighted currents, the proposed waveform generator can output 3 GHz periodic waveforms. The total power consumption is less than 200 mW with a 2.2 V power supply. The total area of the SiGe chip is 1.0 mm2.
In this paper, a modified auto zeroed integrator is used to design and simulate a low-voltage high-speed and accurate switched capacitor pseudo 2-path filter. The filter is a sixth-order Chebyshev band-pass filter operating at sampling frequency of 1MHz and center frequency of 250 kHz with a quality factor of 50. The circuit is simulated using HSPICE and 0.25??m CMOS technology.
B-ISDN is expected to support diverse applications ranging from lowest to highest bit rate communications. In this mode, information is transferred in a connection oriented fashion among communicating entities using fixed size packets know as ATM cell. The Batcher-Banyan combinational switches are one of high speed space division switches. But it finds difficulties in routing two cells with same destination...
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