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For multiplierless FIR filter design and implementation, optimization of the product accumulation block (PAB) in transposed direct form structure has been ignored by most of the research. In this work, the power consumption of the PABs of FIR filters is studied theoretically and experimentally. It is shown that the PAB contributes most of the total power consumption in multiplierless FIR filters....
This paper, formulates a novel technique that explores on-chip IR drop reduction and instantaneous demanded peak-current reduction simultaneously. Proposed solution leverages unused timing slacks, and schedules the clock arrival times to relax the peak current which is delivered through each via-stack in the on-chip IR hot-spots. In addition, this paper formulates and introduces a new evaluation metric...
This paper, presents a novel technique for reducing the intensity of IR hot-spots by leveraging the unused timing slacks to schedule useful skews. The peak current minimization problem is reformulated into a collection of smaller problems of reducing the peak current of each via-stack in the on-chip Power Delivery Network (PDN). In addition to timing information, it considers the PDN and cell placement...
This paper presents a 13-bit fully-differential successive approximation register analog-to-digital converter with a hybrid DAC that is suitable for sensor applications. An innovative dithering plus averaging technique is developed around this originally-designed 10-bit ADC to make it possible to attain an effective resolution of 13 bits in a configurable fashion without calibration. The ADC has a...
Background: Domino logic is widely used in modern digital systems because of easy implementation with less number of transistors and high speed. The pre-charge and evaluation phases of the domino logic, leads to enormous transitions at the output. This switching of the output is undesirable as it leads to more dynamic power dissipation. Methods: This achieved by the using the structures such as True...
This paper present an optimal register alignment for minimization of clock switching scheme in Mesochronous operation. In Mesochronous operation, data are processed in one or more processing clocks based on executing instructions. In this scheme, a delayed clock pulse is allotted for each instruction in the processing unit. Due to different clock frequencies for different instructions, the overhead...
This paper proposes the development of a new digital pulse width modulation (PWM) scheme for aplication to both single phase and multiphase voltage regulation modules (VRMs), which are used as processor power supplies. A comparative analysis of this novel phase accumulator based PWM generation technique is presented with the traditionally used counter based PWM approach for synchronous buck converter...
This paper presents the use of switch-tail ring counter as low transition test pattern generator (TPG) to reduce power consumption in test-per-clock and test-per-scan built-in self-test (BIST) applications. The proposed TPG is implemented by dividing the register in the test mode into many switch-tail ring counters. These counters are fed with a seed in such a way to produce a single transition between...
This paper describes the, design, simulation and implementation of a novel Ultra-fast ‘ripple’ Sorting algorithm. It comprises a dual pipelined, ripple based hardware for sorting numerical data, which can used for real-time applications. The ripple algorithm begins sorting or ranking immediately upon arrival of data at the input. Unlike other sorting algorithms, it does not require storage of all...
The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new poweraware scan segment architecture, which can accurately...
A clock mesh, in which clock signals are shorted at mesh grid, is less susceptible to on-chip process variation, and so it has widely been studied recently for a clock network of smaller skew. A practical design may require more than one mesh primarily because of hierarchical clock gating architecture; a single mesh, however, can also support the same architecture after some hierarchies are removed...
A design of a 10-bit 25 MS/s Successive Approximation Register (SAR) Analog to Digital Converter (ADC) that uses improved dynamic comparator has been introduced in this paper. In this improved dynamic comparator, a novel pre-amplifier is proposed in order to enhance the bandwidth up to 817 MHz when compared to classical pre-amplifier structures. Besides, a modified dynamic latch with driving simultaneously...
This paper presents an SPI interface, a mux-based synchronizer and a DSP block designed for a 2-axis accelerometer IC. The SPI interface is used for writing trim bits to the IC and reading acceleration data. Clock output pin is omitted and data can only be read asynchronously. The synchronizer improves the mean time between failures (MTBF) when multi-bit acceleration data is moved from the domain...
Low power design is gaining prominence due to the increasing need of battery operated portable devices with high computing capability. It is the critical issue in ASIC design, as featured size is scaled down. The reliability of integrated circuit depends on the heat dissipated in the circuit. A large fraction of the power consumed is due to the clock distribution network and the high switching activity...
Memory plays a significant role in successful operations of modern day servers. DDR3 memory has been around for a while and the next generation is almost available. There are lots of challenges which still exist and are not fully uncovered with the DDR3 based ISRDIMMs and discussed in this paper is a unique problem faced during the server memory characterization of ISRDIMMs. Issues were unearthed...
With the increase in the demand for high performance and high speed VLSI systems such as network processors in networking or SOCs in communication and computing has shifted the focus from traditional performance parameters towards the analysis of power consumption. The power budget and management among the domains of a system is of real concern. Hence, the power aware design using clock gating, power...
Cascaded Integrator Comb (CIC) structure is used extensively in the design of a decimation filter. This paper analyses the existing design of decimation filter and proposes a new design with reduced hardware requirements. The designs are modelled using VHDL, simulated using ISim and implemented in Spartan 3E FPGA. The synthesis report shows the reduction in number of I/O bits.
Due to the increasing algorithmic complexity of todays embedded systems, the consideration of extra-functional properties becomes even more important. Extra-functional properties such as timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT- and gate-level, several techniques are available, but there...
Multi-threaded processor designs enable high performance of a single processor core by exploiting both the thread-level and instruction-level parallelism. The performance gain is, however, at the cost of increasing energy consumption, which is not desirable to embedded systems. This paper investigates the energy efficiency of varied multi-threaded processor designs (with the coarse-grained and fine-grained...
Digital sections in several high-precision mixed systems operate at a relatively low frequency, allowing the trading of speed for the mitigation of switching noise and power distribution problems. While the serial clock distribution potentially solves most of these problems, the standard library cells and synthesis tools do not provide much, if any support for the serial clock tree implementation...
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