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Approximate ripple carry adders (RCAs) and carry lookahead adders (CLAs) are presented which are compared with accurate RCAs and CLAs for performing a 32-bit addition. The accurate and approximate RCAs and CLAs are implemented using a 32/28nm CMOS process. Approximations ranging from 4- to 20-bits are considered for the less significant adder bit positions. The simulation results show that approximate...
In this work, we present a radix-16 multi-format multiplier to multiply 64-bit unsigned integer operands, double-precision and single-precision operands. The multiplier is sectioned in two lanes such that two single-precision multiplications can be computed in parallel. Radix-16 is chosen for the reduced number of partial products and the resulting power savings. The experimental results show that...
The vigorous growth in portable multimedia devices and communication system has increased the demand for area and power efficient high-speed Digital Signal Processing (DSP) system. Usage of digital Finite Impulse Response (FIR) filter is one of the prime block in DSP. Digital multipliers and adders are the most critical arithmetic functional units in FIR filters and also decides the performance of...
We propose a new sequential multiplier design that generates the radix-16 partial products (e.g., $P$ ) as two high ($H$ ) and low ($L$ ) components, such that ${P=4H+L}$ , ${H,L\in \{0,~1,~2,~3\}\times X}$ , where ${X}$ denotes the multiplicand. The required hard ${3X}$ multiple is generated in a preliminary cycle to the advantage of reducing the cycle time of the main iteration. Two radix-16...
In this paper we use a 4-bit carry look-ahead adder to highlight the contribution by false-starts (glitches) to overall dynamic power dissipation. These false-starts occur in the generation of the sum outputs and are due to delays in generating and propagating the carry signals. We employ sub-threshold transistor operation in the none critical path and reduce power dissipation by 40%. Post layout...
The addition is the most used arithmetic operation in Digital Signal Processing (DSP) algorithms, such as filters, transforms and predictions. These algorithms are increasingly present in audio and video processing of battery-powered mobile devices having, therefore, energy constraints. In the context of addition operation, the efficient 4-2 adder compressor is capable to performs four additions simultaneously...
ALU is an integral part of the processor. And it is also one of the highest power density location in the processor. Hence in order to optimize the performance of processor, it is important to optimize the ALU. In this paper, proposed ALU having 8 functions has been designed using optimized adder structure. Also, use of pass transistors based multiplexer reduces the transistor count to around 80%...
Reversible gate has been one of the emerging research area that ensure continual process of innovation trends that explore and utilizes the resources. The reversible gate is sparked by its applications in several technologies such as low power CMOS, DNA computing, quantum computing, optical, nanotechnology etc. This paper presents the designing of reversible gate which is used for reversible operation...
The main requirement of Very Large Scale Integration (VLSI) circuit is to be fast and low energy consumption. So, the analysis is done by optimizing the delay, which results in fast processing and low average energy consumed. A 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 90 nm technology. The results from...
In this paper, a review study and analysis of 1-bit full adder designs is presented with different logic styles such as Hybrid pass logic with static CMOS (HPSC), Hybrid and Hybrid-CMOS. Different styles of logic structures are used to design hybrid-CMOS namely pass transistor logic, complementary pass transistor logic (CPL), swing restoration CPL (SR-CPL) etc. So far the hybrid logic style provides...
Compressors form the basic element of arithmetic circuits that are dominated by multi-operand addition operations. Compressor circuits based on carry-save logic have been used in past to realize parallel multipliers for ASIC implementation, however, owing to the peculiar architecture of FPGAs, these circuits do not map well on these platforms. In this paper, FPGA implementation of 4:2 compressor circuit...
In today's system-on-chip designs, a low-drop-out voltage regulator (LDO) is one of the most popular choices to create a distinct voltage domain owing to its high power density. Many LDOs, however, need a large output capacitor (COUT) to compensate a fast load current (ILOAD) change, increasing the number of pins and off-chip components. In synchronous digital LDO designs, high frequency can miniaturize...
Low-power dissipation is an imperative requirement in the design of an efficient Digital Signal Processing system which is employed in many multimedia applications such as image and video processing. Finite Impulse Response (FIR) filter is indispensable in the design of several such Digital Signal Processing (DSP) applications. The output of these applications, either an image or a video can be nearly...
The advancement in IC technology is primarily attributed to the MOSFET scaling theory. As the transistor size reduced, power consumption also reduced. As the process technology reached nano-meter regime, silicon CMOS started developing Short Channel Effects which led to increased power dissipation. A trade-off arose between power-dissipation and area. Alternatives to CMOS were found to avoid the trade-off...
Most important design parameter in integrated circuit is Power dissipation after speed. Adders are one of the basic fundamental component in such circuit, designing much efficient Adder results in optimizing whole circuit. Due to rapid growth in technology there is a need of fast processing arithmetic unit, so Carry Select Adder (CSLA) is one of the fast processing adder. By observing the CSLA circuitry...
The advancement of transistor process technology reduces the chip area at the cost of power consumption. Adiabatic logic is one of the promising low power techniques, which gives low power dissipation at the cost of delay. The proposed work optimizes delay using MOS-GNRFET as the device instead of Si-MOSFET and proposes ECRL logic based 8bit ALU architecture performing 4 arithmetic and 4 logical operations...
Power is one of the most important design parameter after speed, in integrated circuit. One of the basic fundamental component in such circuit is adder and subtractor. In order to optimize such circuits there is need of designing efficient and low power fundamental blocks. As per the Launder's principle, KTln2 heat is dissipated if there is any loss in bit. Excess-3 code is one of the sequential codes...
Now a days, low power Very Large Scale Integration (VLSI) circuit plays an important role in designing efficient energy saving electronic systems for high speed performance. In VLSI, low power dissipation is the main criterion in many electronic devices out of speed, area, etc., like mobile phones, laptops, high speed work stations etc., Due to the integration of many components on the VLSI circuit...
With the increasing complexity of electronic circuits and to meet the demand of high performance, the design and optimization of electronic circuits need to be automated with high degree of reliability and accuracy. In order to optimize hardware requirements of digital combinational circuits, evolutionary and innovative techniques need to be enforced at various levels such as at gate level and device...
This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor...
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