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An original and modern integrated current sensor is designed and presented in this paper. It can provide a sense current proportional to an output current available to the microcontroller via an external resistor. The ratio between output and sense current is modeled and simulated. The errors between the two currents increase in low currents domain. A solution consisting in a gate back regulation...
The 10Gbase-KR protocol is widely used to accomplish the high speed data conversion in the Ethernet area. This paper presents a design of the critical controller in the physical coding sublayer based on the 10Gbase-KR. In order to satisfy the demand of the high speed data conversion, the scrambler and descrambler are specially designed to work in a parallel mode. The post-synthesis simulation results...
This paper investigates the switching performances of two state-of-the-art half-bridge SiC MOSFET modules using a standard double pulse test methodology. A deliberate choice of the modules with the same voltage and current ratings, the same packaging, but different stray inductances and capacitances is made in order to give an insight into the influence of parasitics in the switching transients and...
In this paper, we propose a novel power analysis attack resilient adiabatic logic which, unlike existing secure adiabatic logic designs doesn't require any charge sharing between the output nodes of the gates. The proposed logic also dissipates less energy due to the reduced ON-resistance of the charging path. We investigate and compare our proposed and the existing secure adiabatic logic across a...
In this paper, an optimal gate driving condition between switching loss and surge voltage is investigated by circuit simulation technique. An equivalent circuit model of power semiconductor devices, such as an IGBT and a FWD, are employed. Chip level transient switching waveforms of IGBT at different gate driving condition are calculated and evaluated with measurement results. Evaluation result shows...
This paper presents different experimental methods for measuring parasitic capacitances and inductances of direct copper bond (DBC) based power semiconductor modules. The found parasitics are compared with finite element simulations to evaluate their accuracy. A very good match of the simulated and measured stray capacitances is found. The parasitics, which are found via simulations and experiments,...
This work proposes a new gate driver circuit which utilizes hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) for high-resolution panels. By using one TFT to separate the output node from the capacitor in the gate driver circuit, the driving TFT can remain high speed to pull down the output signal. Simulation results verify that the falling time reduces over 20% without enlarging...
Memristor is considered as one of the promising solutions to the fundamental limitations of the VLSI systems. Logic implementation with memristor device by considering its compatibility with CMOS fabric provides a new vision for digital logic circuits. This work presents a 2 by 2 multiplier cell design using a hybrid CMOS-memristor universal gate. The universal gate based implementation approach is...
Stochastic circuits (SCs) offer tremendous area and power-consumption benefits at the expense of computational inaccuracies. They require random num-ber sources (RNSs) to implement stochastic number generators (SNGs) for all of their inputs. It is common for an SC to have a large number of primary and auxiliary inputs. Often the associated SNGs take up as much as 80% of the entire circuit area, so...
As wireless and telecommunicaton infrastructure communications have been integrated into modern vehicle systems (i.e., infotainment systems and vehicle to vehicle systems), the security implications on the relatively unchanged underlying network protocols inside the vehicles are investigated by researchers and industrial experts in the corresponding domain. Some researchers have achieved the investigation...
A spiking neuron and 3-terminal Resistive RAM (RRAM) model are proposed and simulated as a neural network. The system is analyzed as a complex network of spiking neurons connected by synapses to demonstrate a biologically-inspired associative memory. In recent years, Machine Learning and Artificial Intelligence have become popular fields due to readily available high performance computing systems...
An alternative electrical model for Ion-Sensitive Field-Effect Transistor (ISFET) sensors is presented in this work. The proposed model is worth to be employed in both DC and transient simulations where the behavior of the ISFET sensor coupled to its readout circuit can therefore be investigated. Whereas, previous models found in the literature could only be employed to perform DC simulations. The...
In this paper, a new and simple method named Weibull criterion is proposed to identify whether metastable states occur in single random telegraph noise (RTN), which has been verified by both simulation and experiment results. It is helpful for comprehensive understanding of trap properties and providing a direct evidence of oxide traps with multiple states.
In this paper, an adiabatic based vernier time-to-digital converter (VTDC) is proposed. Generally, static based vernier TDC consumes more power due to two delay chain and D-flipflop. To avoid this issue an adiabatic based vernier TDC is proposed. This proposed TDC is constructed by using adiabatic inverter and D-flipflop but in classical TDC architecture consists of static based inverter and D-flipflop...
A novel electrostatic discharge (ESD) clamp circuit for power-rail ESD protection, consisting of the stacked transistors and biased RC network, is proposed in a 90 nm CMOS process. The biased RC network possesses a small footprint and the detection circuit has a pretty low leakage current of up to 12 nA under normal operation. The proposed ESD clamp circuit has a long hold-on time of 800 ns under...
In this work, we investigate the dual gate positive feedback field-effect transistor (FBFET) using DC and transient TCAD simulation. I-V characteristics, subthreshold swing, and transient characteristics are analyzed. The FBFET has steep switching property and low off current. We design an inverter that can low power operate with the FBFET. By using the FBFET, the stand-by current is effectively suppressed...
A local-feedback transconductor (LFB OTA) is a linear OTA operating in a saturation region. In addition, the LFB OTA operating in a subthreshold region, whose transfer characteristics are expressed by a sinh function, is utilized for low-power and low-transconductance linear OTAs. However, the LFB OTA has a limit of a tuning range of a transconductance because of a local-feedback structure. To improve...
Power electronic applications need high voltage and current ranges which are impossible to obtain with discrete devices. Parallelization technique is a solution to increase power converter current capacity. Current distribution problems may reduce device lifetime and cause converter malfunction. Parallelization requires a total control of circuit parasitic elements which depend on layout physical...
This work presents an ultra-low power low-voltage high-order temperature-compensated voltage reference. The proposed circuit is based on the self-cascode MOSFET (SCM) and explores the dependence of the threshold voltage (VT) with the transistor dimensions. The SCM is biased by the leakage current of a zero-VT transistor for PSRR improvement. The proposed circuit is composed only of 3 transistors....
Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix...
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