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An original and modern integrated current sensor is designed and presented in this paper. It can provide a sense current proportional to an output current available to the microcontroller via an external resistor. The ratio between output and sense current is modeled and simulated. The errors between the two currents increase in low currents domain. A solution consisting in a gate back regulation...
This paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB and 83 μW power consumption in 100kHz bandwidth, which corresponds to FoMw 71fJ/conv.
A U-band oscillator is presented as a divide-by-two direct injection-locked frequency divider (ILFD), with NMOS injection transistors coupled to the LC oscillator. Compared with the both NMOS and PMOS injection transistors, the NMOS only injection transistors contribute to a much wider locking range. The strategy to choose the structure and sizes of the injection transistors for symmetry and the locking...
A new circuit solution for current controlled current amplification is proposed. The basic idea of the circuit is to use a DC current in order to induce an unbalance on the VGS loop of a current mirror. It is demonstrated that the input-output amplification is controlled by a DC current.
This paper presents a 77GHz, 16dBm, 13% PAE power amplifier. It is simulated in a 0.13um silicon-germanium technology with fT of 200GHz. The design technique is not the same as those which are used in traditional power amplifiers. All the matching structures are composed of short or open stubs and MIM capacitors. To get a higher output saturation power, breakdown voltage is also considered in bias...
This paper presents the circuit model that is used for the cross-coupled charge pump design algorithm. Symbolic description of the pump stage model as an analog functional block for high-voltage application is firstly discussed. Design process has been done by using simplified BSIM model equations assuming the long channel MOSFET. Characteristics have been verified by ELDO Spice and compared with...
In this paper, a new electronically controllable current-mode instrumentation amplifier (CMIA) is presented. The proposed CMIA is based on only two electronically tunable second-generation current conveyors (ECCIIs). It does not need any passive element which makes it highly suitable for integration. More interestingly, high CMRR is achieved without the need for matching between active elements. Its...
In this paper, we propose a novel power analysis attack resilient adiabatic logic which, unlike existing secure adiabatic logic designs doesn't require any charge sharing between the output nodes of the gates. The proposed logic also dissipates less energy due to the reduced ON-resistance of the charging path. We investigate and compare our proposed and the existing secure adiabatic logic across a...
Noise of the charge pump degrades the in-band phase noise of charge pump phase-locked loop (CPPLL). This paper analyzes the noise mechanism of a bipolar junction transistor based charge pump and validates the analysis through simulation, providing necessary insight into the design of low-noise charge pump for CPPLL-based frequency synthesizers. A simple model for bipolar transistor noise is utilized...
In this paper, a low-power four-quadrant current multiplier based on the electronically and linearly tunable CMOS transconductors (EOTAs) is presented. The design technique is realized by using only two EOTAs as active circuit elements. The proposed current multiplier can operate for four quadrants with wide input dynamic range. The performances of the proposed current multiplier are tested on PSPICE...
This paper presents a novel circuit implementation for overcurrent protection of low-dropout voltage regulators, that is able to limit the maximum current the regulator can source into the load to a value set by the user and to keep the current limit value fairly independent of process variation and output voltage, as well as maintaining its temperature drift over the wide temperature range of −50°C...
This work presents an ultra-low power low-voltage high-order temperature-compensated voltage reference. The proposed circuit is based on the self-cascode MOSFET (SCM) and explores the dependence of the threshold voltage (VT) with the transistor dimensions. The SCM is biased by the leakage current of a zero-VT transistor for PSRR improvement. The proposed circuit is composed only of 3 transistors....
In this paper the simple method to reduce the switching energy of capacitive digital-to-analog converters (DACs) in low-power successive approximation register (SAR) analog-to-digital converters (ADCs) is described. The method is based on the well-known monotonic switching procedure and the use of one intermediate voltage level during switching. Unlike most recently published switching methods the...
This paper presents a novel startup circuit that provides a startup operation for bias circuits and reference circuits. The proposed circuit employs delay buffer and series transistors to automatically turn off the startup circuit after the bias circuit has started. Thus, the proposed startup circuit consumes no power during the normal operation of the reference circuit and is useful for low-power...
An external capacitor-less low dropout (LDO) voltage regulator with high PSRR and enhanced transient response is presented. The novel idea is applying a replica circuit which can pull excessive current. Excessive Current Pulling (ECP) technique decreases the equivalent output impedance to enhance transient response. The proposed LDO has been simulated in 0.18 μm CMOS Technology. Its regulated output...
Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix...
In present work is carried out modelling of single transistor parallel ZVS DC-DC converter. Main advantage of power circuit is direct work in steady mode. Thus, that allows avoiding a starting procedure and guarantees reliable operation in significant major change in load occur. The model is realised with Matlab. Computer simulations and experiments in lab model are performed by which the model is...
In this paper, we propose a 1-bit Full Adder circuit built with Ballistic Deflection Transistors (BDT). BDT is a disruptive technology based on AlGaAs/InGaAs heterostructure. Different combinational circuits were successfully realized using BDT NAND gate and General Purpose Gate (GPG) structures. The developed circuit is an extension of BDT GPG and different from that of the previously implemented...
This paper presents novel circuit techniques to implement DDR I/O circuit design that can support multiple low-power standards in a state-of-art 7nm CMOS finfet process. Hybrid pull-up driver with a power gating switch is proposed to support a wide range of data rates and output swing levels. The usage of both thin and thick gate oxide devices in the final output stage effectively achieves minimal...
Operation analysis and synthesis of the coordinated rotation system based on the two-speed induction motors (IM) with cage rotors presented. The circuit uses a transistor voltage controller to maintain the speed of IM. The second group of IM windings is used for parametrical synchronization, while transistor controller is used to compensate for the residual error. Transfer functions of the original...
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