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This paper reports a novel differential Colpitts LC oscillator circuit topology designed in 28 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. It exploits magnetic coupling between the spirals of the LC tank, in order to enhance the equivalent quality factor (Q). The oscillator circuit topology presented here shows a potential for achieving a high spectral purity at the mm-wave frequency...
This paper reports a novel voltage-controlled oscillator (VCO) circuit topology based on a transformer-coupled π network. As a case study, the proposed VCO circuit topology has been designed and studied for 60 GHz applications for emerging 5th generation wireless communications. Overall, the presented VCO circuit topology is characterized by low phase noise (−91 dBc/Hz at a 1 MHz frequency offset...
This paper reports a novel differential Hartley oscillator circuit topology. The circuit topology exploits the transformer coupling to enhance the effective quality factor (Q) of the LC tank and shows a potential for achieving a high spectral purity at the mm-wave frequency range. The oscillator topology has been designed for 60 GHz in 28 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology.
A novel class-AB Flipped Voltage Follower is proposed, suitable for low-voltage low-power CMOS implementation in advanced technology nodes. Simulations have been performed using STMicroelectronics models for the 45nm technology. The Flipped Voltage Follower allows low output impedance and high linearity by means of a feedback loop. However, like the conventional common-drain voltage follower, it has...
In this paper we show that the area optimization of STT-MRAM bitcells can deliver a substantial reduction in the energy per write access when dynamic voltage scaling (DVS) is adopted. Indeed, the increase in the bitcell area enables the reduction in the write energy consumed by the bitcells at the expense of the energy of peripheral circuits, when lowering the supply voltage. The proposed approach...
In this paper, an 8-channel area-efficient low-power current-mode analog front-end amplifier (AFEA) is designed for EEG signal recording. The AFEA is composed of eight capacitive coupled transconductors (CCGMs), current-mode band-pass filters (CMBPFs), and programmable current-gain amplifiers (PCGAs) with a multiplexer (MUX), a transimpedance amplifier (TIA), and an offset current cancellation loop...
It has been shown in the literature that a cross-coupled CMOS LC VCO will outperform an equivalent Colpitts VCO. In the case of bipolar devices, the jury is still out. This paper reports a comparative analysis of phase noise (PN), tuning range (TR), dissipated DC power and Figure of Merit (FoM) in cross-coupled and differential Colpitts LC VCOs topologies designed in 180 nm Si-Ge HBT technology for...
In this conference paper, the voltage differencing buffered amplifier (VDBA) based three different grounded inductance simulators are proposed. The proposed circuits are lossless inductance simulator, serial R-L and parallel R-L inductance simulators. The proposed inductance simulators are employed single active element and two or three passive components. To test performance of the inductance simulators,...
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
Researchers have predicted the end of the Moore law. One of the reasons is that MOS bulk transistor is reaching its limits: Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Threshold Voltage (Vth) and Vdd scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Up to now, the industrial solutions focus on silicon CMOS technology...
In this paper we present extremely small size integrated balun topologies in 65 nm CMOS technology for millimeter wave applications. An octagon stacked version of the transformer balun and respectively, a stacked version of the Marchand balun are proposed. Both balun structures are designed for 60 GHz applications and present a wideband performance, satisfactory phase and amplitude imbalances. The...
This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and employs one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns...
This paper presents a 56Gb/s 16-QAM 65nm CMOS transceiver using a W-band carrier. Two wideband IF signals are up- and downconverted simultaneously with 68GHz and 102GHz carriers. The transceiver achieves 56Gb/s data-rate with TX-to-RX EVM of −16.5dB within 0.1m distance. The transceiver consumes 260mW and 300mW from a 1V supply in TX and RX modes, respectively. This results in 10pJ/bit efficiency,...
In this paper single operational transresistance amplifier based lossless grounded negative inductance simulator topology is presented. The proposed circuit employs only single OTRA and four passive elements. The circuit is studied for nonideality and high frequency self compensation is achieved. Theoretical propositions are verified by simulation.
Sigma-Delta Analog-to-Digital converter (ADC), is widely used in portable electronic products. An operational transconductance amplifier (OTA) is one of the most important components of this ADC. This paper reports a new design of low power fully differential OTA. In this design authors have used adaptive biasing technique and DC gain enhancement technique for improving design parameters as compared...
An S band octave bandwidth bandpass filter with loss compensation in 0.13 μm CMOS is presented. The minimum inductor filter topology is employed which is suitable for lumped element CMOS filters at low GHz frequencies. This filter benefits from the minimum number of inductors which results in less loss, smaller size, and lower cost. To further improve the filter performance, single-ended negative...
A set of low noise transimpedance amplifiers manufactured and characterized in CMOS and BiCMOS technologies is proposed in this work. Layout optimization, efficient modelling and bias point optimization are the techniques employed to reduce the input noise current density. The CMOS amplifiers were designed to work at 10 Gbps. The BiCMOS amplifiers, based on HBT transistors, can operate at bit rates...
In this paper continuous time high-performance current mirrors (CMs) based on series and parallel connected unity sized CMOS transistors suitable for low power applications are presented. It is shown that the proposed implementation techniques allow an increased output resistance, from twice the output resistance of the simple current mirror (SCM) up to more than 50 times of the cascode current mirror's...
With the emergence of energy-starved systems like wireless sensor nodes, it becomes much more of a necessity for important blocks in such systems like the voltage reference (VR) to work at an ultra-low power consumption. Furthermore, the varying requirements of the functional blocks of a wireless sensor node (WSN) entail varying VR requirements, therefore flexibility in the design of VRs is required...
In this paper, a simple filter topology that can be used to implement first-order MOS-only allpass filter is proposed. The proposed MOS-only allpass filter offers inherently very accurate magnitude and phase characteristics at very high frequencies. However, MOS-only active filter suffers from an inherent low frequency limitation. In order to address this issue, the modification technique allowing...
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