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This paper presents a low voltage and power efficient 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed adaptive time-domain (ATD) comparator automatically adjusts its input-referred noise performance according to the intermediate residual input level (ΔVin) during conversion. Considering the noise requirement of 12-bit SAR ADC, the proposed implementation...
A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the...
This paper proposes the reconfigurable RX analog baseband transformer that supports multi-standard applications. The proposed ABB can transform its structure between a delta-sigma modulated ADC for narrow band and a baseband LPF for wide band with a simple switch configuration without extra cost. Thus, the ABB obtains efficiency in both size and power aspects. It occupies only 0.11mm2 of active area...
This paper presents a novel circuit configuration of a vector-sum phase shifter for millimeter-wave beamforming to lower power consumption. The proposed configuration has a 90-degree hybrid circuit and two zero-pi amplifiers. The zero-pi amplifiers have a zero-pi phase switching function and a variable amplitude control function. The zero-pi phase switching function is achieved by switching two input...
In this paper, we present a new beacon recognition method for wireless sensor devices to access beacon-enabled WSN with low-power consumption. At first, we explain necessity of the low-power beacon recognition in the beacon-enabled wireless sensor networks. By realigning network resources, we catch that beacons are in the same position in each BI (beacon interval). Then, we propose how to switch operation...
The article designed a military grade switchboard with Gigabit POE power capacity through 5 ports by researching switch principle and actual requirement. Firstly, the whole circuit and associated systems were introduced. Secondly, the circuit which used network management chip 88E6161 of Marvel Company and microcontroller chip PD69104B of Micro-semi Company was designed and emulated, the specific...
This paper presents a regenerative sampling oscillator for the simultaneous regeneration of phase and amplitude, which enables highly efficient QAM schemes in the mm-wave range to reach multi-Gb/s data rates. A nonlinear model is derived to study the phase regeneration and the startup behavior of the oscillator and is simulated in CADENCE. A cross-coupled circuit is fabricated in a 0.13-μm SiGe BiCMOS...
Scan shift power consumption is one of the major concerns in low power circuits. While there are multiple design for testability (DFT) techniques proposed in the literature for addressing both peak and average shift power optimization, most of the solutions impose additional design overhead which may impact functional performance of the device. In this paper, we propose a novel frequency scaled segmented...
A novel concept instrumentation amplifier (IA) using an analog signal compression technique is suggested to achieve a large dynamic input range. A large analog input signal is segmented into a smaller analog signal to prevent saturating the analog output signal in the input stage of the IA. At the input stage, we apply a reference bias at a node between an input capacitor and an input MOS to function...
As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power. We employ a power analysis framework and load profiles that provide accurate power figures. Furthermore, we analyze the power behavior in normal operation...
A new power estimation approach based on the decomposition of a digital system into basic operators is presented. This approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated...
This work presents a System-on-Chip designed for Energy-Harvested applications. It embeds an ARM® Cortex®-M0+ microcontroller, 4KB RAM, 4KB ROM, an ultra-low power frequency synthesizer, a custom power switch, and a Power Management Unit enabling Active and Sleep modes. The system fabricated in 28 nm FD-SOI technology achieves 2.7pJ/cycle at 16 MHz during active mode, and the core consumes 4.3 nW...
In this paper we present a new architecture for thermometer-coded digital-to-analog converters (DAC) that are used as a part of segmented DACs. The size of the binary-to-thermometer decoder tends to grow relatively large compared to the DAG when the number of input bits increases. We propose an architecture that utilizes PMOS current source transistor and moves the switching logic inside the current...
More integration in the transmission chain for an ultrasound system moves the study of new possible solutions to reduce the area and simply the system. A sixteen channels 5 levels high-voltage transmitter device and a 64 high-voltage switches device for ultrasound medical imaging system are reported. The pulser device takes advantage of 16 analog channels able to provide +/-100V driven by 2 independent...
Price-based demand response programs have recently become focus of interest due to the increased flexibility and potential to deliver greater demand responsiveness. However, the key to success of such programs highly depends on greater participation of residential customers through defining more effective dynamic tariffs. This paper aims to assess and predict the probability of switching between different...
This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network to cover an input range twice the reference voltage. The ADC's loading effect to previous stage...
Online energy-efficient real-time task scheduling for a heterogeneous multicore system is complicated because of the synergistic processing between cores and trade-off between energy conservation and schedulability. This paper proposes a multicore energy efficiency ratio for minimizing energy consumption and a bandwidth reservation algorithm for improving quality of service for applications. The performance...
Resistive crossbar arrays show significant improvement in terms of energy and area efficiency when compared to current SRAM based memory technologies. However, due to its resistive nature, it suffers from undesired current sneak-paths complicating read-out procedures. In this paper, we present a voltage-based reading technique in resistive memories. The simplicity of the readout circuit enables parallel...
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which...
For multiplierless FIR filter design and implementation, optimization of the product accumulation block (PAB) in transposed direct form structure has been ignored by most of the research. In this work, the power consumption of the PABs of FIR filters is studied theoretically and experimentally. It is shown that the PAB contributes most of the total power consumption in multiplierless FIR filters....
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