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This paper reports on a signal-propagation loss through two human bodies in wearable-to-wearable intra-body communication. We investigated the signal propagation through two human bodies for expanding the two-person intra-body communication services. We estimated a detected signal power through human bodies was obtained by an experiment and simulation. The detected signal power through two human bodies...
A concept of universal broadband (1.5–4.5 GHz) receiver SoC is proposed. It makes the design and production of variety of digitally controlled receivers for different sub-bands of L- and S-bands more simple, fast and cheap. The design and measurements of broadband RF IP-blocks for the SoC based on 0.25 μm SiGe BiCMOS process are presented: digital step attenuator with serial/parallel control driver,...
This paper presents a dual-channel GNSS receiver covering GPS and Beidou on a single chip in 0.13μm CMOS process. The receiver incorporates one reconfigurable RF front-end and two separate IF signal channels with one single fractional-N frequency synthesizer by using a ring voltage-controlled oscillator. This architecture supports an external active or passive antenna and provides the benefits of...
In whole system, the user usually only offers a voltage with noise as input logic voltage to digital receiver, to guarantee the right logic control, it requires that the IC chip must have a stable inversion level with logic high and logic low input voltage. For COMS process, in traditional design scheme, it usually uses a normal digital inverter as input-unit schematic, and changes the width or length...
Internet of Things (IoT) is a topic of growing interest and intensive research in industry, technological centers and academy, where data communication is one of its most relevant aspects. Since IoT is an open field for new applications, it does not have yet a standard communication protocol. This paper presents the system level design of a WiFi receiver supporting the novel low power standard IEEE...
This paper reviews a set of architecture and circuit techniques that have enabled data rates beyond 10Gb/s, and explores a range of design challenges and considerations as we move to higher data rates. In particular, we review ADC-based designs and their challenges and tradeoffs, including ADC resolution, oversampling ratio, and power consumption.
This paper presents a 60 GHz low gain imbalance low noise amplifier (LNA)-phase shifter (PS) in 65 nm CMOS for phased-array receiver. The proposed LNA-PS consists of an LNA and PS. The LNA with 1-stage current steering cascode provides 1-dB step 2-bit gain control with almost constant phase response. Thus, gain imbalance of the 4-bit PS is compensated. The LNA-PS is optimized for a phased-array receiver...
An 80 Gb/s 4-level pulse amplitude modulation (PAM4) wireline receiver is presented in this paper. This receiver adopts quarter rate architecture to improve data rate and reduce power consumption. In order to reduce the complexity of the clock and data recovery (CDR) design, a voltage control oscillator (VCO) based CDR without reference clock is used. Furthermore, four BBPDs are used to sample the...
Molecular Communication (MC) is a new multidisciplinary subject concerning medicine, biology, and communication engineering. MC concept is introduced for modeling of communication of nano/micro scale devices. In MC systems, chemical signals carrying information in gaseous or liquid media are used. Similar to other communication systems, in MC sending information from transmitter to receiver with minimum...
Wireless interconnects are capable of establishing energy-efficient intra and inter-chip data communications. This paper introduces a circuit level design of an energy-efficient millimeter-wave (mm-wave) non-coherent on-off keying (OOK) receiver suitable for such wireless interconnects in 45-nm CMOS process. The receiver consists of a simple two-stage common source structure based Low Noise Amplifier...
In this article a millimetre-wave (mm-wave) down-converter based on a six-port correlator and zero bias Schottky diode is presented over 10 GHz bandwidth, from 72 to 82 GHz. The six-port is designed in such a way to have excellent phase resolution at four output ports witch leads to very accurate symbol position for QPSK demodulator. A prototype circuit has been manufactured with miniaturized hybrid...
Wireless or contactless electrical energy transfer is a method of utilizing electromagnetic induction to transfer electrical power from the source (transmitter) to the loads (receivers) without using the conventional media, such as wires. This method had been investigated since end of 18 century, and Nikola Tesla was the first scientist to realize it. The development of technology increases the usage...
Photonic-electronic integration is a key technology to master data traffic growth and therefore an enabler of future network technologies. For some time now, a novel silicon-based photonic-electronic integration technology, photonic BiCMOS, is under development at IHP. Photonic BiCMOS is a planar technology co-integrating monolithically on a single substrate high-speed RF frontend electronics - by...
This work presents an inductor-less 0.4 V cellular receiver (RX) front-end with an ultra-low power of 10 mW and an ultra-small area 0.31 mm2 in 16 nm FinFET technology, which enables massive receivers in a single chip for 10 Gb/s high throughput 5G system in sub-6 GHz band. The proposed inductor-less low-Vdd RX front-end consists of an LNA, passive mixers, LO generator and 20MHz bandwidth channel...
This paper presents an ultra-low power, high-sensitivity, and interference-resistant receiver suitable for IoT applications. By the combination of sliding-IF based low-power down-conversion and relative-power-detection based FSK demodulation, the proposed receiver achieves multi-channel operation and minimizes power consumption. Cascaded N-path filter and 4th-order hybrid-PPF are adopted to improve...
An IEEE 802.11ah-compliant RF transceiver with a direct-conversion receiver and a fully-digital polar transmitter is presented. For the receiver, a current-mode RF front-end covers the mandatory modes worldwide from 755MHz to 928MHz. The digitally-assisted analog baseband achieves variable gains and bandwidths with an automatic gain/DC-offset calibration. Implemented in 40nm CMOS with 1V supply, this...
The Radiated emission measurement is one of the tests required in EMC testing. CISPR 25 standard specifies the frequency range and the antennas used for this purpose. In this paper, differences that appear when using different measurement antennas and different semi-anechoic chambers in radiated emissions testing on the same DUT are investigated. Results show sometimes significant differences that...
Increasing the number of electric/electronic devices powered with electric power, has led to a series of different chargers and a mixture of wires spread through the house or office. For a long period of time, the concept of charging without any direct connection through wires was avoided, but the last few years show an increased interest to make the loading with electrical power more flexible and...
A wideband cellular RF receiver for multi-band carrier aggregation employing a current-efficient wideband low noise amplifier and a frequency-band switchable transformer is demonstrated in a 14nm FinFET CMOS technology. The proposed wideband low-noise amplifier can support multiple-channel RF signals for intra-band carrier aggregation with high performance and low DC current consumption. Moreover,...
This paper presents a 65 nm CMOS 25–30 GHz hybrid beamforming receiver with eight antenna inputs and two baseband output streams. The receiver uses the Cartesian-Combining architecture, which is introduced for two baseband streams. Each antenna signal is complex-weighted independently and combined with weighted signals from other antennas prior to downconversion. Each RF-domain complex weight is realized...
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