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The Trustful Space-Time Protocol (TSTP) allows for time synchronization to be performed upon receiving any message from another node in a sensor network, removing the need for explicit synchronization messages. Previous work has shown that TSTP performs well under controlled experimental environments. In this work, we analyze how the quality of synchronization in TSTP is affected when nodes are communicating...
Physically Unclonable Functions (PUFs) offer enticing possibilities to incorporate hardware-based security on semiconductor device level. In order to make efficient use of PUF functionality in lightweight cryptographic applications, a low-overhead implementation in terms of chip area and power consumption is required. In this paper a fully differential readout circuit is proposed that allows the generation...
The influence of 1,5 um Rad-hard CMOS process parameters (gate oxide growth temperature and chemical environment) variations on the total ionizing dose effects is comparatively analyzed in experiment on the build-in test structures. The optimal process parameter set is found as a compromise between IC functionality and radiation hardness.
This paper analyzes the sensitivity of five standard logic gates (AND, OR, INV, NAND and NOR) to Single Event Transients (SETs). All gates have been designed in IHP's 130 nm bulk CMOS technology. The analysis was conducted with SPICE simulations, employing the current injection concept to model the SET effects. The SET sensitivity of the investigated logic gates was evaluated in terms of critical...
The quality of TRNG designs mainly depends on the grade of the noise source from which the entropy will be harvested to extract randomness. Especially for purely digital noise sources suitable for FPGA implementations the use of Ring Oscillators is suggested in many scientific publications. Standard Ring Oscillator based noise sources however have earned some criticism regarding the amount of entropy...
A fully synthesizable analog-like loop filter for a Low-Dropout regulator using only digital standard cells is proposed. To accommodate this, various blocks such as comparator, time-to-digital converter and charge-pumps are developed using only standard cells. The fabricated prototype in 0.13μm process occupying 0.0875mm2 provides 15mA current with minimum quiescent current of 140μA and load transient...
Logic gates for ultra-low voltages suffer from speed and robustness degradations, which are highly associated with the process technology. In this work a methodology for the automated design-space exploration of standard logic gates for a 28 nm FD-SOI technology is shown. Comprehensive design space explorations of inverter and nand2 gates show the benefits of back-biasing at sub-threshold supply voltages...
Data processing performed by adder circuits need to achieve low delay and low power at the same time while maintaining low cost, due to the steep growth in mobile computation devices. Recently proposed 1-bit full adder design that hybridizes transmission gates (TG) and standard CMOS offers significant PDP improvement. Two full adder implementations are presented in this paper which further optimizes...
This work is focused on a technique providing the integration of the method of clustered voltage scaling (CVS) in the digital design flow. The efficiency of this technique in the case of a hashing unit IP-block is considered. In order to reduce the power consumption special hash algorithms (NH, PH) in combination with the CVS approach were proposed. For the implementation of the CVS technique a number...
A silicon carbide (SiC) vertical field effect transistor (VJFET) with ultra-low feedback capacitance Crss has been developed, which is called as screen grid VJFET (SG-VJFET). The SG-VJFET is a very promising power device because of the superior static characteristics such as normally off, low on-resistance, and high breakdown voltage, furthermore, issueless in terms of gate oxide reliability and long-term...
The standard LSTM recurrent neural networks while very powerful in long-range dependency sequence applications have highly complex structure and relatively large (adaptive) parameters. In this work, we present empirical comparison between the standard LSTM recurrent neural network architecture and three new parameter-reduced variants obtained by eliminating combinations of the input signal, bias,...
Outsourcing designs to 3rd party vendors is a common practice in the integrated circuit (IC) manufacturing industry. This outsourcing brings advantages such as lower manufacturing cost and shorter time-to-market for a new system, which at the same time raises security threats in the IPs from 3rd party vendors. These IPs may contain hardware Trojans capable of compromising the product's confidentiality,...
Digital circuit design may demand critical requirements, such as power consumption, robustness, performance, etc., while being implemented in VLSI (Very Large Scale Integration). The asynchronous paradigm presents interesting features that serve as an alternative to these critical requirements. An important class of the asynchronous paradigm is the one called QDI (Quasi Delay Insensitive) circuits...
Low Power Wide Area Networks (LPWAN) are expected to interconnect a high number of simple and inexpensive devices. The ability to control transmission parameters including modulation scheme and output power, enables reduction of the deployment costs, improvement of the network reliability, in terms of error performance under suboptimal conditions, and could contribute to the reduction of the maintenance...
This paper focus on the design of Programmable Logic BIST structures for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing. The advancements happening in VLSI technology day by day have made chip testing more complicated. This has paved way for the increased popularity of Logic Built In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST allows self testing of...
In this paper, we provide an efficient method to improve the subthreshold characteristic of silicon-on-insulator (SOI) MOSFET using a vertical non-uniform doping profile for the drain region. Two different structures are simulated: uniform-drain (UD) and gaussian-drain (GD) SOI MOSFET and results are compared. Gaussian distribution function parameters such as peak doping density (Np) and standard...
A surface layer formation by Cs+ bombardment was observed during ultra-thin oxynitride gate dielectrics depth profiling. A significant thickness change relative to ultra-thin layer of oxynitride was noticed when testing a bombarded sample after a period of time. Cs, O and N depth profiles were examined by Dynamic Secondary Ion Mass Spectrometry (DSIMS). The bombarded sample and new sample were investigated...
This paper presents a smart system based on Low Power Wide Area networks for a remote monitoring of technological room in unstaffed railway stations. The paper aim is the design of an efficient network scheme characterized by improved performance compared with the standard solution. Adopting an innovative smart System Control Strategy and a custom network topology, good results are reached in terms...
The IoT/M2M service providers need security mechanisms to avoid illegal usage of the service. Normally, this can be accomplished by using the certificate to authenticate the device before providing the service. In this paper, we consider the situation where a malicious user attempts to pay only for the service of a device but deploy the same certificate for many other devices to access the service...
Training convolutional networks (CNNs) that fit on a single GPU with minibatch stochastic gradient descent has become effective in practice. However, there is still no effective method for training large networks that do not fit in the memory of a few GPU cards, or for parallelizing CNN training. In this work we show that a simple hard mixture of experts model can be efficiently trained to good effect...
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